公开(公告)号：US20110186988A1

公开(公告)日：2011-08-04

申请号：US12700004

申请日：2010-02-04

申请人： Chih-Hua Chen ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Tzuan-Horng Liu

发明人： Chih-Hua Chen ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Tzuan-Horng Liu

IPC分类号： H01L23/485 ,  H01L23/498

CPC分类号： H01L24/11 ,  H01L23/485 ,  H01L23/498 ,  H01L23/49811 ,  H01L24/27 ,  H01L2224/05552 ,  H01L2924/14 ,  H01L2924/35121 ,  H01L2924/365 ,  H01L2924/00012 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor chip having a first region and a second region; a dielectric layer formed on the first region and the second region of the semiconductor chip; a first elongated under-bump metallization (UBM) connector formed in the dielectric layer and on the first region of the semiconductor chip and having a first longer axis extending in a first direction; and a second elongated UBM connector formed in the dielectric layer on the second region of the semiconductor chip and having a second longer axis extending in a second direction. The first direction is different from the second direction.

摘要翻译： 集成电路结构包括具有第一区域和第二区域的半导体芯片; 形成在半导体芯片的第一区域和第二区域上的电介质层; 形成在所述电介质层中且在所述半导体芯片的所述第一区域上并且具有沿第一方向延伸的第一长轴的第一细长凹凸金属化（UBM）连接器; 以及第二细长UBM连接器，其形成在所述半导体芯片的所述第二区域上的所述电介质层中，并且具有沿第二方向延伸的第二长轴。 第一个方向与第二个方向不同。

公开(公告)号：US07514797B2

公开(公告)日：2009-04-07

申请号：US11756347

申请日：2007-05-31

申请人： Chen-Shien Chen ,  Kai-Ming Ching ,  Chih-Hua Chen ,  Chen-Cheng Kuo

发明人： Chen-Shien Chen ,  Kai-Ming Ching ,  Chih-Hua Chen ,  Chen-Cheng Kuo

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/76898 ,  H01L24/02 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/50 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04073 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2518 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2224/48145 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor die package is provided. The semiconductor die package includes a plurality of dies arranged in a stacked configuration. Through-silicon vias are formed in the lower or intermediate dies to allow electrical connections to dies stacked above. The lower die is positioned face up and has redistribution lines electrically coupling underlying semiconductor components to the through-silicon vias. The dies stacked above the lower die may be oriented face up such that the contact pads are facing away from the lower die or flipped such that the contact pads are facing the lower die. The stacked dies may be electrically coupled to the redistribution lines via wire bonding or solder balls. Additionally, the lower die may have another set of redistribution lines on an opposing side from the stacked dies to reroute the vias to a different pin-out configuration.

摘要翻译： 提供半导体管芯封装。 半导体管芯封装包括以堆叠构造布置的多个管芯。 在下部或中间模具中形成通孔，以允许电连接到上面堆叠的管芯。 下模具面向上放置并具有将下面的半导体部件电耦合到通硅通孔的再分配线。 堆叠在下模具上方的模具可以朝上取向，使得接触焊盘背离下模或翻转，使得接触焊盘面向下模。 堆叠的管芯可以通过引线接合或焊球电耦合到再分配线。 此外，下模具可以在与堆叠的管芯相对的一侧上具有另一组重新分布线，以将通孔重新路由到不同的引脚配置。

公开(公告)号：US20080283959A1

公开(公告)日：2008-11-20

申请号：US11803783

申请日：2007-05-16

申请人： Chen-Shien Chen ,  Chen-Cheng Kuo ,  Kai-Ming Ching ,  Chih-Hua Chen

发明人： Chen-Shien Chen ,  Chen-Cheng Kuo ,  Kai-Ming Ching ,  Chih-Hua Chen

IPC分类号： H01L23/52

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a substrate; a through-silicon via (TSV) in the substrate, the TSV being tapered; a hard mask region extending from a top surface of the substrate into the substrate, wherein the hard mask encircles a top portion of the TSV; dielectric layers over the substrate; and a metal post extending from a top surface of the dielectric layers to the TSV, wherein the metal post comprises same materials as the TSV.

摘要翻译： 集成电路结构包括：基板; 在衬底中的穿硅通孔（TSV），TSV是锥形的; 从所述基板的顶表面延伸到所述基板中的硬掩模区域，其中所述硬掩模围绕所述TSV的顶部; 衬底上的介电层; 以及从电介质层的顶表面延伸到TSV的金属柱，其中金属柱包括与TSV相同的材料。

公开(公告)号：US09679836B2

公开(公告)日：2017-06-13

申请号：US13298102

申请日：2011-11-16

申请人： Ching-Wen Hsiao ,  Ming-Da Cheng ,  Chih-Wei Lin ,  Chen-Shien Chen ,  Chih-Hua Chen ,  Chen-Cheng Kuo

发明人： Ching-Wen Hsiao ,  Ming-Da Cheng ,  Chih-Wei Lin ,  Chen-Shien Chen ,  Chih-Hua Chen ,  Chen-Cheng Kuo

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L21/683 ,  H01L25/10 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/49816 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/105 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/014 ,  H01L2924/00

摘要： A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A solder region is disposed in the polymer region and electrically coupled to the redistribution line. The solder region includes a second flat top surface not higher than the first flat top surface.

公开(公告)号：US20130119539A1

公开(公告)日：2013-05-16

申请号：US13298102

申请日：2011-11-16

申请人： Ching-Wen Hsiao ,  Ming-Da Cheng ,  Chih-Wei Lin ,  Chen-Shien Chen ,  Chih-Hua Chen ,  Chen-Cheng Kuo

发明人： Ching-Wen Hsiao ,  Ming-Da Cheng ,  Chih-Wei Lin ,  Chen-Shien Chen ,  Chih-Hua Chen ,  Chen-Cheng Kuo

IPC分类号： H05K1/11 ,  H01L21/60 ,  H01L23/485

CPC分类号： H01L23/49816 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/105 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/014 ,  H01L2924/00

摘要： A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A solder region is disposed in the polymer region and electrically coupled to the redistribution line. The solder region includes a second flat top surface not higher than the first flat top surface.

摘要翻译： 一种装置包括再分布线，以及在再分配线上模制的聚合物区域。 聚合物区域包括第一平坦顶表面。 焊料区域设置在聚合物区域中并电耦合到再分配线路。 焊料区域包括不高于第一平坦顶表面的第二平坦顶表面。

公开(公告)号：US08193639B2

公开(公告)日：2012-06-05

申请号：US12750468

申请日：2010-03-30

申请人： Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

发明人： Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

IPC分类号： H01L23/485

CPC分类号： H01L23/585 ,  H01L23/552 ,  H01L23/562 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/13655 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor chip, a metal pad at a major surface of the semiconductor chip, and an under-bump metallurgy (UBM) over and contacting the metal pad. A metal bump is formed over and electrically connected to the UBM. A dummy pattern is formed at a same level, and formed of a same metallic material, as the metal pad.

摘要翻译： 集成电路结构包括半导体芯片，在半导体芯片的主表面处的金属焊盘和在凸块下金属（UBM）上并与金属焊盘接触的集成电路结构。 金属凸块形成在UBM上并与UBM电连接。 在同一水平上形成虚拟图案，并由与金属垫相同的金属材料形成。

公开(公告)号：US07785927B2

公开(公告)日：2010-08-31

申请号：US12392918

申请日：2009-02-25

申请人： Chen-Shien Chen ,  Kai-Ming Ching ,  Chih-Hua Chen ,  Chen-Cheng Kuo

发明人： Chen-Shien Chen ,  Kai-Ming Ching ,  Chih-Hua Chen ,  Chen-Cheng Kuo

IPC分类号： H01L21/98

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/76898 ,  H01L24/02 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/50 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04073 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2518 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2224/48145 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor die package is provided. The semiconductor die package includes a plurality of dies arranged in a stacked configuration. Through-silicon vias are formed in the lower or intermediate dies to allow electrical connections to dies stacked above. The lower die is positioned face up and has redistribution lines electrically coupling underlying semiconductor components to the through-silicon vias. The dies stacked above the lower die may be oriented face up such that the contact pads are facing away from the lower die or flipped such that the contact pads are facing the lower die. The stacked dies may be electrically coupled to the redistribution lines via wire bonding or solder balls. Additionally, the lower die may have another set of redistribution lines on an opposing side from the stacked dies to reroute the vias to a different pin-out configuration.

摘要翻译： 提供半导体管芯封装。 半导体管芯封装包括以堆叠构造布置的多个管芯。 在下部或中间模具中形成通孔，以允许电连接到上面堆叠的管芯。 下模具面向上放置并具有将下面的半导体部件电耦合到通硅通孔的再分配线。 堆叠在下模具上方的模具可以朝上取向，使得接触焊盘背离下模或翻转，使得接触焊盘面向下模。 堆叠的管芯可以通过引线接合或焊球电耦合到再分配线。 此外，下模具可以在与堆叠的管芯相对的一侧上具有另一组重新分布线，以将通孔重新路由到不同的引脚配置。

公开(公告)号：US20090269905A1

公开(公告)日：2009-10-29

申请号：US12495124

申请日：2009-06-30

申请人： Chen-Shien Chen ,  Chen-Cheng Kuo ,  Kai-Ming Ching ,  Chih-Hua Chen

发明人： Chen-Shien Chen ,  Chen-Cheng Kuo ,  Kai-Ming Ching ,  Chih-Hua Chen

IPC分类号： H01L21/762 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a substrate; a through-silicon via (TSV) in the substrate, the TSV being tapered; a hard mask region extending from a top surface of the substrate into the substrate, wherein the hard mask encircles a top portion of the TSV; dielectric layers over the substrate; and a metal post extending from a top surface of the dielectric layers to the TSV, wherein the metal post comprises same materials as the TSV.

摘要翻译： 集成电路结构包括：基板; 在衬底中的穿硅通孔（TSV），TSV是锥形的; 从所述基板的顶表面延伸到所述基板中的硬掩模区域，其中所述硬掩模围绕所述TSV的顶部; 衬底上的介电层; 以及从电介质层的顶表面延伸到TSV的金属柱，其中金属柱包括与TSV相同的材料。

公开(公告)号：US07564115B2

公开(公告)日：2009-07-21

申请号：US11803783

申请日：2007-05-16

申请人： Chen-Shien Chen ,  Chen-Cheng Kuo ,  Kai-Ming Ching ,  Chih-Hua Chen

发明人： Chen-Shien Chen ,  Chen-Cheng Kuo ,  Kai-Ming Ching ,  Chih-Hua Chen

IPC分类号： H01L29/00

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a substrate; a through-silicon via (TSV) in the substrate, the TSV being tapered; a hard mask region extending from a top surface of the substrate into the substrate, wherein the hard mask encircles a top portion of the TSV; dielectric layers over the substrate; and a metal post extending from a top surface of the dielectric layers to the TSV, wherein the metal post comprises same materials as the TSV.

摘要翻译： 集成电路结构包括：基板; 在衬底中的穿硅通孔（TSV），TSV是锥形的; 从所述基板的顶表面延伸到所述基板中的硬掩模区域，其中所述硬掩模围绕所述TSV的顶部; 衬底上的介电层; 以及从电介质层的顶表面延伸到TSV的金属柱，其中金属柱包括与TSV相同的材料。

公开(公告)号：US20090155957A1

公开(公告)日：2009-06-18

申请号：US12392918

申请日：2009-02-25

申请人： Chen-Shien Chen ,  Kai-Ming Ching ,  Chih-Hua Chen ,  Chen-Cheng Kuo

发明人： Chen-Shien Chen ,  Kai-Ming Ching ,  Chih-Hua Chen ,  Chen-Cheng Kuo

IPC分类号： H01L21/98

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/76898 ,  H01L24/02 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/50 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04073 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2518 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2224/48145 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor die package is provided. The semiconductor die package includes a plurality of dies arranged in a stacked configuration. Through-silicon vias are formed in the lower or intermediate dies to allow electrical connections to dies stacked above. The lower die is positioned face up and has redistribution lines electrically coupling underlying semiconductor components to the through-silicon vias. The dies stacked above the lower die may be oriented face up such that the contact pads are facing away from the lower die or flipped such that the contact pads are facing the lower die. The stacked dies may be electrically coupled to the redistribution lines via wire bonding or solder balls. Additionally, the lower die may have another set of redistribution lines on an opposing side from the stacked dies to reroute the vias to a different pin-out configuration.

摘要翻译： 提供半导体管芯封装。 半导体管芯封装包括以堆叠构造布置的多个管芯。 在下部或中间模具中形成通孔，以允许电连接到上面堆叠的管芯。 下模具面向上放置并具有将下面的半导体部件电耦合到通硅通孔的再分配线。 堆叠在下模具上方的模具可以朝上取向，使得接触焊盘背离下模或翻转，使得接触焊盘面向下模。 堆叠的管芯可以通过引线接合或焊球电耦合到再分配线。 此外，下模具可以在与堆叠的管芯相对的一侧上具有另一组重新分布线，以将通孔重新路由到不同的引脚配置。