公开(公告)号：US08193639B2

公开(公告)日：2012-06-05

申请号：US12750468

申请日：2010-03-30

申请人： Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

发明人： Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

IPC分类号： H01L23/485

CPC分类号： H01L23/585 ,  H01L23/552 ,  H01L23/562 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/13655 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor chip, a metal pad at a major surface of the semiconductor chip, and an under-bump metallurgy (UBM) over and contacting the metal pad. A metal bump is formed over and electrically connected to the UBM. A dummy pattern is formed at a same level, and formed of a same metallic material, as the metal pad.

摘要翻译： 集成电路结构包括半导体芯片，在半导体芯片的主表面处的金属焊盘和在凸块下金属（UBM）上并与金属焊盘接触的集成电路结构。 金属凸块形成在UBM上并与UBM电连接。 在同一水平上形成虚拟图案，并由与金属垫相同的金属材料形成。

公开(公告)号：US08546941B2

公开(公告)日：2013-10-01

申请号：US12700004

申请日：2010-02-04

申请人： Chih-Hua Chen ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Tzuan-Horng Liu

发明人： Chih-Hua Chen ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Tzuan-Horng Liu

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L23/485 ,  H01L23/498 ,  H01L23/49811 ,  H01L24/27 ,  H01L2224/05552 ,  H01L2924/14 ,  H01L2924/35121 ,  H01L2924/365 ,  H01L2924/00012 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor chip having a first region and a second region; a dielectric layer formed on the first region and the second region of the semiconductor chip; a first elongated under-bump metallization (UBM) connector formed in the dielectric layer and on the first region of the semiconductor chip and having a first longer axis extending in a first direction; and a second elongated UBM connector formed in the dielectric layer on the second region of the semiconductor chip and having a second longer axis extending in a second direction. The first direction is different from the second direction.

摘要翻译： 集成电路结构包括具有第一区域和第二区域的半导体芯片; 形成在半导体芯片的第一区域和第二区域上的电介质层; 形成在所述电介质层中且在所述半导体芯片的所述第一区域上并且具有沿第一方向延伸的第一长轴的第一细长凹凸金属化（UBM）连接器; 以及形成在所述半导体芯片的所述第二区域上的所述电介质层中并具有在第二方向上延伸的第二长轴的第二细长UBM连接器。 第一个方向与第二个方向不同。

公开(公告)号：US20110241202A1

公开(公告)日：2011-10-06

申请号：US12750468

申请日：2010-03-30

申请人： Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

发明人： Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

IPC分类号： H01L23/485

CPC分类号： H01L23/585 ,  H01L23/552 ,  H01L23/562 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/13655 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor chip, a metal pad at a major surface of the semiconductor chip, and an under-bump metallurgy (UBM) over and contacting the metal pad. A metal bump is formed over and electrically connected to the UBM. A dummy pattern is formed at a same level, and formed of a same metallic material, as the metal pad.

摘要翻译： 集成电路结构包括半导体芯片，在半导体芯片的主表面处的金属焊盘和在凸块下金属（UBM）上方并接触金属焊盘。 金属凸块形成在UBM上并与UBM电连接。 在同一水平上形成虚拟图案，并由与金属垫相同的金属材料形成。

公开(公告)号：US20110186988A1

公开(公告)日：2011-08-04

申请号：US12700004

申请日：2010-02-04

申请人： Chih-Hua Chen ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Tzuan-Horng Liu

发明人： Chih-Hua Chen ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Tzuan-Horng Liu

IPC分类号： H01L23/485 ,  H01L23/498

CPC分类号： H01L24/11 ,  H01L23/485 ,  H01L23/498 ,  H01L23/49811 ,  H01L24/27 ,  H01L2224/05552 ,  H01L2924/14 ,  H01L2924/35121 ,  H01L2924/365 ,  H01L2924/00012 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor chip having a first region and a second region; a dielectric layer formed on the first region and the second region of the semiconductor chip; a first elongated under-bump metallization (UBM) connector formed in the dielectric layer and on the first region of the semiconductor chip and having a first longer axis extending in a first direction; and a second elongated UBM connector formed in the dielectric layer on the second region of the semiconductor chip and having a second longer axis extending in a second direction. The first direction is different from the second direction.

摘要翻译： 集成电路结构包括具有第一区域和第二区域的半导体芯片; 形成在半导体芯片的第一区域和第二区域上的电介质层; 形成在所述电介质层中且在所述半导体芯片的所述第一区域上并且具有沿第一方向延伸的第一长轴的第一细长凹凸金属化（UBM）连接器; 以及第二细长UBM连接器，其形成在所述半导体芯片的所述第二区域上的所述电介质层中，并且具有沿第二方向延伸的第二长轴。 第一个方向与第二个方向不同。

公开(公告)号：US08753971B2

公开(公告)日：2014-06-17

申请号：US13427430

申请日：2012-03-22

申请人： Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

发明人： Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

IPC分类号： H01L21/44

CPC分类号： H01L23/585 ,  H01L23/552 ,  H01L23/562 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/13655 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

摘要： A method of forming an integrated circuit structure is provided. The method includes forming a metal pad at a major surface of a semiconductor chip, forming an under-bump metallurgy (UBM) over the metal pad such that the UBM and the metal pad are in contact, forming a dummy pattern at a same level as the metal pad, the dummy pattern formed of a same metallic material as the metal pad and electrically disconnected from the metal pad, and forming a metal bump over the UBM such that the metal bump is electrically connected to the UBM and no metal bump in the semiconductor chip is formed over the dummy pattern.

摘要翻译： 提供一种形成集成电路结构的方法。 该方法包括在半导体芯片的主表面上形成金属焊盘，在金属焊盘上形成凸块下冶金（UBM），使得UBM和金属焊盘接触，形成与 金属焊盘，由与金属焊盘相同的金属材料形成的虚拟图案，并与金属焊盘电气断开，并在UBM上形成金属凸块，使得金属凸块电连接到UBM，并且在金属焊盘中没有金属凸块 在虚拟图案上形成半导体芯片。

公开(公告)号：US20120178252A1

公开(公告)日：2012-07-12

申请号：US13427430

申请日：2012-03-22

申请人： Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

发明人： Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

IPC分类号： H01L21/768

CPC分类号： H01L23/585 ,  H01L23/552 ,  H01L23/562 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/13655 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

摘要： A method of forming an integrated circuit structure is provided. The method includes forming a metal pad at a major surface of a semiconductor chip, forming an under-bump metallurgy (UBM) over the metal pad such that the UBM and the metal pad are in contact, forming a dummy pattern at a same level as the metal pad, the dummy pattern formed of a same metallic material as the metal pad and electrically disconnected from the metal pad, and forming a metal bump over the UBM such that the metal bump is electrically connected to the UBM and no metal bump in the semiconductor chip is formed over the dummy pattern.

摘要翻译： 提供一种形成集成电路结构的方法。 该方法包括在半导体芯片的主表面上形成金属焊盘，在金属焊盘上形成凸块下冶金（UBM），使得UBM和金属焊盘接触，形成与 金属焊盘，由与金属焊盘相同的金属材料形成的虚拟图案，并与金属焊盘电气断开，并在UBM上形成金属凸块，使得金属凸块电连接到UBM，并且在金属焊盘中没有金属凸块 在虚拟图案上形成半导体芯片。

公开(公告)号：US08659170B2

公开(公告)日：2014-02-25

申请号：US12905276

申请日：2010-10-15

申请人： Chen-Cheng Kuo ,  Tzuan-Horng Liu ,  Chen-Shien Chen

发明人： Chen-Cheng Kuo ,  Tzuan-Horng Liu ,  Chen-Shien Chen

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/44

CPC分类号： H01L24/06 ,  H01L21/76838 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/0501 ,  H01L2224/0502 ,  H01L2224/05085 ,  H01L2224/05099 ,  H01L2224/0556 ,  H01L2224/05599 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/15787 ,  H01L2224/13099 ,  H01L2224/05552 ,  H01L2924/00

摘要： A semiconductor device includes at least two conductive pads, one of the conductive pads being formed above another of the at least two conductive pads, and a redistribution layer extending from at least one of the conductive pads. The semiconductor device also includes a bump structure formed over the conductive pads and electrically coupled to the conductive pads.

摘要翻译： 半导体器件包括至少两个导电焊盘，其中一个导电焊盘形成在至少两个导电焊盘的另一个之上，以及从至少一个导电焊盘延伸的再分配层。 半导体器件还包括形成在导电焊盘上并且电耦合到导电焊盘的凸块结构。

公开(公告)号：US08765497B2

公开(公告)日：2014-07-01

申请号：US13225113

申请日：2011-09-02

申请人： Hao-Juin Liu ,  Chita Chuang ,  Ching-Wen Hsiao ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Chih-Hua Chen

发明人： Hao-Juin Liu ,  Chita Chuang ,  Ching-Wen Hsiao ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Chih-Hua Chen

IPC分类号： H01L21/66 ,  H01L23/00 ,  H01L23/48

CPC分类号： H01L22/20 ,  H01L22/14 ,  H01L23/3128 ,  H01L23/48 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method includes placing a plurality of bottom units onto a jig, wherein the plurality of bottom units is not sawed apart and forms an integrated component. Each of the plurality of bottom units includes a package substrate and a die bonded to the package substrate. A plurality of upper component stacks is placed onto the plurality of bottom units, wherein solder balls are located between the plurality of upper component and the plurality of bottom units. A reflow is performed to join the plurality of upper component stacks with respective ones of the plurality of bottom units through the solder balls.

摘要翻译： 一种方法包括将多个底部单元放置在夹具上，其中多个底部单元没有锯切并形成一个集成部件。 多个底部单元中的每一个包括封装基板和结合到封装基板的管芯。 多个上部组件堆放在多个底部单元上，其中焊球位于多个上部组件和多个底部单元之间。 执行回流以通过焊球将多个上部部件堆叠与多个底部单元中的相应的底部单元接合。

公开(公告)号：US08202800B2

公开(公告)日：2012-06-19

申请号：US13112347

申请日：2011-05-20

申请人： Chih-Hua Chen ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Wen-Wei Shen

发明人： Chih-Hua Chen ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Wen-Wei Shen

IPC分类号： H01L21/44

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a through silicon via (TSV) structure includes forming an interconnect pad over a substrate. An under layer is formed over the interconnect pad. A vertical conductive post is formed at least partially through the substrate. At least one dummy structure is formed at least partially through the under layer. A top pad is formed over the dummy structure and the vertical conductive post. The top pad covers a wider area than a cross section of the vertical conductive post. The interconnect pad is electrically connected to the top pad. The dummy structure connects the top pad and the under layer thereby fastening the top pad and the interconnect pad.

摘要翻译： 形成贯穿硅通孔（TSV）结构的方法包括在衬底上形成互连焊盘。 在互连焊盘上形成下层。 至少部分地穿过衬底形成垂直导电柱。 至少部分地通过底层形成至少一个虚拟结构。 顶部衬垫形成在虚拟结构和垂直导电柱上。 顶部焊盘覆盖比垂直导电柱的横截面更宽的区域。 互连焊盘电连接到顶部焊盘。 虚拟结构连接顶部焊盘和下层，从而紧固顶部焊盘和互连焊盘。

公开(公告)号：US08178970B2

公开(公告)日：2012-05-15

申请号：US12623925

申请日：2009-11-23

申请人： Wen-Wei Shen ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Chih-Hua Chen ,  Ching-Wen Hsiao

发明人： Wen-Wei Shen ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Chih-Hua Chen ,  Ching-Wen Hsiao

IPC分类号： H01L23/488

CPC分类号： H01L24/16 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13005 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/812 ,  H01L2224/814 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/381 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/206 ,  H01L2924/207

摘要： A flip-chip packaging assembly and integrated circuit device are disclosed. An exemplary flip-chip packaging assembly includes a first substrate; a second substrate; and joint structures disposed between the first substrate and the second substrate. Each joint structure comprises an interconnect post between the first substrate and the second substrate and a joint solder between the interconnect post and the second substrate, wherein the interconnect post exhibits a width and a first height. A pitch defines a distance between each joint structure. The first height is less than half the pitch.

摘要翻译： 公开了一种倒装芯片封装组件和集成电路器件。 示例性的倒装芯片封装组件包括第一基板; 第二基板; 以及设置在第一基板和第二基板之间的接合结构。 每个接头结构包括在第一基板和第二基板之间的互连柱和在互连柱和第二基板之间的接合焊料，其中互连柱呈现宽度和第一高度。 间距定义每个关节结构之间的距离。 第一高度小于音高的一半。