公开(公告)号：US07936243B2

公开(公告)日：2011-05-03

申请号：US11488608

申请日：2006-07-19

申请人： Ying-Jiunn Lai ,  Chang-Sheng Chen ,  Chin-Sun Shyu ,  Uei-Ming Jow ,  Chang-Lin Wei

发明人： Ying-Jiunn Lai ,  Chang-Sheng Chen ,  Chin-Sun Shyu ,  Uei-Ming Jow ,  Chang-Lin Wei

IPC分类号： H01F27/28

CPC分类号： H01C17/23 ,  H01C7/003 ,  H05K1/167 ,  H05K3/0047 ,  H05K2203/171 ,  H05K2203/175

摘要： An adjustable resistor embedded in a multi-layered substrate and method for forming the same. The adjustable resistor comprises: a planar resistor, having a plurality of terminals; and a plurality of connecting lines connected to the planar resistor, each of the connecting lines being drawn from each of the terminals of the planar resistor so as to form a resistor network, wherein the connecting lines are selectively broken by a process for drilling the substrate to form a number of combinations of opened connecting lines such that the resistance value of the adjustable resistor is varied and thus the resistance value of the adjustable resistor can be precisely adjusted.

摘要翻译： 嵌入多层基板中的可调电阻及其形成方法。 可调电阻器包括：具有多个端子的平面电阻器; 以及连接到平面电阻器的多个连接线，每个连接线从平面电阻器的每个端子拉出以形成电阻器网络，其中通过用于钻取基板的工艺来选择性地断开连接线 以形成打开的连接线的多个组合，使得可调节电阻器的电阻值变化，从而可以精确地调节可调电阻器的电阻值。

公开(公告)号：US07528433B2

公开(公告)日：2009-05-05

申请号：US11456094

申请日：2006-07-07

申请人： Uei-Ming Jow ,  Chang-Sheng Chen ,  Ying-Jiunn Lai ,  Chin-Sun Shyu

发明人： Uei-Ming Jow ,  Chang-Sheng Chen ,  Ying-Jiunn Lai ,  Chin-Sun Shyu

IPC分类号： H01L29/00

CPC分类号： H05K1/162 ,  H01G4/232 ,  H01G4/306 ,  H01L23/50 ,  H01L23/5223 ,  H01L28/10 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/09672 ,  H01L2924/00

摘要： A capacitor structure with a cross-coupling design is provided. In the capacitor structure, conductive lines or electrode plates are coupled together by cross coupling an electrode above or below or aside the other electrode. By cross coupling and fewer vias, the largest capacitance value can be obtained within a minimum area. The capacitor structure provided can also be applied to a high-frequency high-speed module or system to enhance noise inhibition capability of a capacitive substrate.

摘要翻译： 提供了具有交叉耦合设计的电容器结构。 在电容器结构中，通过在另一电极上方或下方或旁边交叉耦合电极将导线或电极板耦合在一起。 通过交叉耦合和较少的通孔，可以在最小区域内获得最大的电容值。 所提供的电容器结构也可以应用于高频高速模块或系统，以增强电容性基板的噪声抑制能力。

公开(公告)号：US07515435B2

公开(公告)日：2009-04-07

申请号：US11646339

申请日：2006-12-28

申请人： Uei-Ming Jow ,  Chang-Sheng Chen ,  Chin-Sun Shyu ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Ying-Jiunn Lai

发明人： Uei-Ming Jow ,  Chang-Sheng Chen ,  Chin-Sun Shyu ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Ying-Jiunn Lai

IPC分类号： H05K1/16

CPC分类号： H01L23/14 ,  H01F17/0006 ,  H01F41/046 ,  H01F2017/0066 ,  H01G4/30 ,  H01G4/40 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49894 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/162 ,  H05K1/165 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/086 ,  H05K2201/09672 ,  H01L2924/00

摘要： A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.

摘要翻译： 提供了多功能复合基板结构。 具有高介电常数的第一衬底和具有低介电常数和低损耗角正切的第二衬底交错在第三衬底之上。 可以在每个衬底上方形成一个或多个磁导块，从而可以在其上制造一个或多个电感器。 可以在第一基板上制造一个或多个电容器。 此外，系统阻抗的一个或多个信号传输迹线形成在外层的第二基板上。 因此，有效地提高了电感器的电感。 此外，内置组件的面积减少。 此外，它具有更短的延迟时间，更小的介电损耗和更高的传输高速和高频信号的回波损耗。

公开(公告)号：US20070133182A1

公开(公告)日：2007-06-14

申请号：US11438363

申请日：2006-05-23

申请人： Chang-Sheng Chen ,  Uei-Ming Jow ,  Ying-Jiunn Lai ,  Chin-Sun Shyu

发明人： Chang-Sheng Chen ,  Uei-Ming Jow ,  Ying-Jiunn Lai ,  Chin-Sun Shyu

IPC分类号： H05K7/00

CPC分类号： H05K1/162 ,  H03H7/09 ,  H03H7/1775 ,  H03H2001/0085 ,  H05K3/4626 ,  H05K3/4688 ,  H05K2201/09236 ,  H05K2201/09672

摘要： A multi-layered printed circuit board embedded with a filter, the multi-layered printed circuit board using a composite multi-layered printed circuit board formed of at least a high dielectric material stacked with at least a low dielectric material. A plurality of serial or parallel capacitors are disposed in the composite multi-layered printed circuit board so as to form a filter. At least one capacitor is an interdigital capacitor disposed on a low dielectric material. Metal electrodes of the interdigital capacitor are located on the same plane such that the area of the metal electrodes or the spacing between the metal electrodes can be adjusted in advance to precisely control the electrical properties such as the center frequency and the transmission loss of the filter. Problems resulting from alignment errors caused in manufacturing the composite multi-layered printed circuit board can also be prevented.

摘要翻译： 嵌入滤光器的多层印刷电路板，使用由至少由至少低介电材料层叠的高介电材料形成的复合多层印刷电路板的多层印刷电路板。 多个串联或并联电容器设置在复合多层印刷电路板中以形成滤波器。 至少一个电容器是设置在低电介质材料上的叉指电容器。 叉指电容器的金属电极位于同一平面上，使得金属电极的面积或金属电极之间的间隔可以预先调整以精确地控制诸如滤波器的中心频率和传输损耗之类的电气特性 。 也可以防止在制造复合多层印刷电路板时引起的对准误差所引起的问题。

公开(公告)号：US08049512B2

公开(公告)日：2011-11-01

申请号：US11882814

申请日：2007-08-06

申请人： Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lai ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Ying-Jiunn Lai

发明人： Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lai ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Ying-Jiunn Lai

IPC分类号： G01R31/11

CPC分类号： G01R31/2818 ,  G01R31/2813 ,  G01R31/2839 ,  H05K1/0268 ,  H05K1/0298 ,  H05K1/16 ,  H05K3/46 ,  H05K2203/162 ,  Y10T29/49004

摘要： A circuit board with embedded components includes a plurality of embedded components and at least one transmission line electrically connected to at least one of the embedded components and having a terminal circuit. Therefore, a measuring device is used to be electrically connected to the transmission line and send out a signal, so as to receive a corresponding reflected signal, and then, compare the received reflected signal with a signal pattern in the database to obtain an electrical parameter of the embedded component.

摘要翻译： 具有嵌入式组件的电路板包括多个嵌入式组件和至少一个电连接到至少一个嵌入式组件并具有终端电路的传输线。 因此，使用测量装置电连接到传输线并发出信号以接收对应的反射信号，然后将接收的反射信号与数据库中的信号模式进行比较，以获得电参数 的嵌入式组件。

公开(公告)号：US08035036B2

公开(公告)日：2011-10-11

申请号：US11861297

申请日：2007-09-26

申请人： Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Ying-Jiunn Lai

发明人： Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Ying-Jiunn Lai

IPC分类号： H05K1/16

CPC分类号： H05K1/167 ,  H05K1/0224 ,  H05K1/025 ,  H05K1/0298 ,  H05K2201/0792 ,  H05K2201/09681 ,  H05K2201/0969

摘要： A complementary mirror image embedded planar resistor architecture is provided. In the architecture, a complementary hollow structure is formed on a ground plane or an electrode plane to minimize the parasitic resistance, so as to efficiently enhance the application frequency. In addition, in some cases, some signal transmission lines pass through the position below the embedded planar resistor, and if there is no shield at all, serious interference or cross talk phenomenon occurs. Therefore, the complementary hollow structure of the ground plane, the electrode plane, or a power layer adjacent to the embedded planar resistor is designed to be a mesh structure, so as to reduce the interference or cross talk phenomenon. In this manner, the whole resistor structure has preferable high frequency electrical characteristic in the circuit.

摘要翻译： 提供了一种互补镜像嵌入式平面电阻架构。 在该结构中，在接地平面或电极平面上形成互补的中空结构以最小化寄生电阻，从而有效地提高施加频率。 此外，在某些情况下，一些信号传输线通过嵌入式平面电阻器下方的位置，如果根本没有屏蔽，则会发生严重的干扰或串扰现象。 因此，将接地平面，电极平面或与嵌入式平面电阻器相邻的功率层的互补空心结构设计为网格结构，以减少干扰或串扰现象。 以这种方式，整个电阻器结构在电路中具有优选的高频电特性。

公开(公告)号：US20070222552A1

公开(公告)日：2007-09-27

申请号：US11488608

申请日：2006-07-19

申请人： Ying-Jiunn Lai ,  Chang-Sheng Chen ,  Chin-Sun Shyu ,  Uei-Ming Jow ,  Chang-Lin Wei

发明人： Ying-Jiunn Lai ,  Chang-Sheng Chen ,  Chin-Sun Shyu ,  Uei-Ming Jow ,  Chang-Lin Wei

IPC分类号： H01C1/012

CPC分类号： H01C17/23 ,  H01C7/003 ,  H05K1/167 ,  H05K3/0047 ,  H05K2203/171 ,  H05K2203/175

摘要： An adjustable resistor embedded in a multi-layered substrate and method for forming the same. The adjustable resistor comprises: a planar resistor, having a plurality of terminals; and a plurality of connecting lines connected to the planar resistor, each of the connecting lines being drawn from each of the terminals of the planar resistor so as to form a resistor network, wherein the connecting lines are selectively broken by a process for drilling the substrate to form a number of combinations of opened connecting lines such that the resistance value of the adjustable resistor is varied and thus the resistance value of the adjustable resistor can be precisely adjusted.

摘要翻译： 嵌入多层基板中的可调电阻及其形成方法。 可调电阻器包括：具有多个端子的平面电阻器; 以及连接到平面电阻器的多个连接线，每个连接线从平面电阻器的每个端子拉出以形成电阻器网络，其中通过用于钻取基板的工艺来选择性地断开连接线 以形成打开的连接线的多个组合，使得可调节电阻器的电阻值变化，从而可以精确地调节可调电阻器的电阻值。

公开(公告)号：US20070164396A1

公开(公告)日：2007-07-19

申请号：US11646339

申请日：2006-12-28

申请人： Uei-Ming Jow ,  Chang-Sheng Chen ,  Chin-Sun Shyu ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Ying-Jiunn Lai

发明人： Uei-Ming Jow ,  Chang-Sheng Chen ,  Chin-Sun Shyu ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Ying-Jiunn Lai

IPC分类号： H01L29/00

CPC分类号： H01L23/14 ,  H01F17/0006 ,  H01F41/046 ,  H01F2017/0066 ,  H01G4/30 ,  H01G4/40 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49894 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/162 ,  H05K1/165 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/086 ,  H05K2201/09672 ,  H01L2924/00

摘要： A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.

摘要翻译： 提供了多功能复合基板结构。 具有高介电常数的第一衬底和具有低介电常数和低损耗角正切的第二衬底交错在第三衬底之上。 一个或多个导磁块可以形成在每个衬底之上，使得可以在其上制造一个或多个电感器。 可以在第一基板上制造一个或多个电容器。 此外，系统阻抗的一个或多个信号传输迹线形成在外层的第二基板上。 因此，有效地提高了电感器的电感。 此外，内置组件的面积减少。 此外，它具有更短的延迟时间，更小的介电损耗和更高的传输高速和高频信号的回波损耗。

公开(公告)号：US20100226112A1

公开(公告)日：2010-09-09

申请号：US12783478

申请日：2010-05-19

申请人： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

发明人： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

IPC分类号： H05K9/00

CPC分类号： H05K1/0218 ,  H05K1/0224 ,  H05K1/0237 ,  H05K1/025 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K2201/0792 ,  H05K2201/09672

摘要： A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented.

摘要翻译： 提供一种镜像屏蔽结构，其包括电子元件和电子元件下方的接地屏蔽平面。 接地屏蔽面的形状与电子元件的突出形状相同，接地屏蔽面的水平尺寸大于或等于电子元件的尺寸。 因此，有效地减小了电子元件与接地屏蔽层之间的寄生效应，并且电子元件之间的垂直耦合效应也降低。 此外，防止了由传输线的布局引起的对嵌入元件的信号完整性的垂直影响。

公开(公告)号：US07764512B2

公开(公告)日：2010-07-27

申请号：US11451292

申请日：2006-06-12

申请人： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

发明人： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

IPC分类号： H05K7/18

CPC分类号： H05K1/0218 ,  H05K1/0224 ,  H05K1/0237 ,  H05K1/025 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K2201/0792 ,  H05K2201/09672

摘要： A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented.

摘要翻译： 提供一种镜像屏蔽结构，其包括电子元件和电子元件下方的接地屏蔽平面。 接地屏蔽面的形状与电子元件的突出形状相同，接地屏蔽面的水平尺寸大于或等于电子元件的尺寸。 因此，有效地减小了电子元件与接地屏蔽层之间的寄生效应，并且电子元件之间的垂直耦合效应也降低。 此外，防止了由传输线的布局引起的对嵌入元件的信号完整性的垂直影响。