公开(公告)号：US06297095B1

公开(公告)日：2001-10-02

申请号：US09596399

申请日：2000-06-16

申请人： Ramachandran Muralidhar ,  Chitra K. Subramanian ,  Sucharita Madhukar ,  Bruce E. White ,  Michael A. Sadd ,  Sufi Zafar ,  David L. O'Meara ,  Bich-Yen Nguyen

发明人： Ramachandran Muralidhar ,  Chitra K. Subramanian ,  Sucharita Madhukar ,  Bruce E. White ,  Michael A. Sadd ,  Sufi Zafar ,  David L. O'Meara ,  Bich-Yen Nguyen

IPC分类号： H01L21336

CPC分类号： H01L21/28282 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/66439 ,  H01L29/7888

摘要： A semiconductor memory device with a floating gate that includes a plurality of nanoclusters (21) and techniques useful in the manufacturing of such a device are presented. The device is formed by first providing a semiconductor substrate (12) upon which a tunnel dielectric layer (14) is formed. A plurality of nanoclusters (19) is then grown on the tunnel dielectric layer (14). After growth of the nanoclusters (21), a control dielectric layer (20) is formed over the nanoclusters (21). In order to prevent oxidation of the formed nanoclusters (21), the nanoclusters (21) may be encapsulated using various techniques prior to formation of the control dielectric layer (20). A gate electrode (24) is then formed over the control dielectric (20), and portions of the control dielectric, the plurality of nanoclusters, and the gate dielectric that do not underlie the gate electrode are selectively removed. After formation of spacers (35), source and drain regions (32, 34) are then formed by implantation in the semiconductor layer (12) such that a channel region is formed between the source and drain regions (32, 34) underlying the gate electrode (24).

摘要翻译： 提出了一种具有浮动栅极的半导体存储器件，其包括多个纳米团簇（21）和用于制造这种器件的技术。 该器件通过首先提供其上形成有隧道介电层（14）的半导体衬底（12）形成。 然后在隧道介电层（14）上生长多个纳米团簇（19）。 在纳米团簇（21）生长之后，在纳米团簇（21）上形成控制电介质层（20）。 为了防止形成的纳米团簇（21）的氧化，可以在形成控制电介质层（20）之前使用各种技术将纳米团簇（21）进行封装。 然后在控制电介质（20）上形成栅极（24），并且选择性地去除不在栅电极下面的控制电介质，多个纳米团簇和栅极电介质的部分。 在形成间隔物（35）之后，然后通过注入在半导体层（12）中形成源极和漏极区域（32,34），使得沟道区域形成在栅极下面的源极和漏极区域（32,34）之间 电极（24）。

公开(公告)号：US08785310B2

公开(公告)日：2014-07-22

申请号：US13427343

申请日：2012-03-22

申请人： Toshio Hasegawa ,  Kunihiro Tada ,  Hideaki Yamasaki ,  David L. O'Meara ,  Gerrit J. Leusink

发明人： Toshio Hasegawa ,  Kunihiro Tada ,  Hideaki Yamasaki ,  David L. O'Meara ,  Gerrit J. Leusink

IPC分类号： H01L21/44

CPC分类号： H01L21/76898 ,  C23C16/42 ,  C23C16/45538 ,  H01L21/28518 ,  H01L21/28562 ,  H01L28/91 ,  H01L29/66181

摘要： A method is provided for forming a metal silicide layer on a substrate. According to one embodiment the method includes providing the substrate in a process chamber, exposing the substrate at a first substrate temperature to a plasma generated from a deposition gas containing a metal precursor, where the plasma exposure forms a conformal metal-containing layer on the substrate in a self-limiting process. The method further includes exposing the metal-containing layer at a second substrate temperature to a reducing gas in the absence of a plasma, where the exposing steps are alternatively performed at least once to form the metal silicide layer, and the deposition gas does not contain the reducing gas. The method provides conformal metal silicide formation in deep trenches with high aspect ratios.

摘要翻译： 提供了一种在衬底上形成金属硅化物层的方法。 根据一个实施例，该方法包括在处理室中提供衬底，将衬底在第一衬底温度下暴露于由含有金属前体的沉积气体产生的等离子体，其中等离子体暴露在衬底上形成保形金属含有层 在一个自限制的过程中。 该方法还包括在不存在等离子体的情况下将第二衬底温度下的含金属层暴露于还原气体，其中暴露步骤交替进行一次以形成金属硅化物层，并且沉积气体不含 还原气。 该方法提供了具有高纵横比的深沟槽中的保形金属硅化物形成。

公开(公告)号：US20130196505A1

公开(公告)日：2013-08-01

申请号：US13427343

申请日：2012-03-22

申请人： Toshio Hasegawa ,  Kunihiro Tada ,  Hideaki Yamasaki ,  David L. O'Meara ,  Gerrit J. Leusink

发明人： Toshio Hasegawa ,  Kunihiro Tada ,  Hideaki Yamasaki ,  David L. O'Meara ,  Gerrit J. Leusink

IPC分类号： H01L21/3205

CPC分类号： H01L21/76898 ,  C23C16/42 ,  C23C16/45538 ,  H01L21/28518 ,  H01L21/28562 ,  H01L28/91 ,  H01L29/66181

摘要： A method is provided for forming a metal silicide layer on a substrate. According to one embodiment the method includes providing the substrate in a process chamber, exposing the substrate at a first substrate temperature to a plasma generated from a deposition gas containing a metal precursor, where the plasma exposure forms a conformal metal-containing layer on the substrate in a self-limiting process. The method further includes exposing the metal-containing layer at a second substrate temperature to a reducing gas in the absence of a plasma, where the exposing steps are alternatively performed at least once to form the metal silicide layer, and the deposition gas does not contain the reducing gas. The method provides conformal metal silicide formation in deep trenches with high aspect ratios.

摘要翻译： 提供了一种在衬底上形成金属硅化物层的方法。 根据一个实施例，该方法包括在处理室中提供衬底，将衬底在第一衬底温度下暴露于由包含金属前体的沉积气体产生的等离子体，其中等离子体暴露在衬底上形成保形的含金属层 在一个自限制的过程中。 该方法还包括在不存在等离子体的情况下将第二衬底温度下的含金属层暴露于还原气体，其中暴露步骤交替进行一次以形成金属硅化物层，并且沉积气体不含 还原气。 该方法提供了具有高纵横比的深沟槽中的保形金属硅化物形成。

公开(公告)号：US07479454B2

公开(公告)日：2009-01-20

申请号：US10674703

申请日：2003-09-30

申请人： David L. O'Meara ,  Daniel Craig Burdett ,  Stephen H. Cabral ,  Gert Leusink ,  John William Kostenko ,  Cory Wajda

发明人： David L. O'Meara ,  Daniel Craig Burdett ,  Stephen H. Cabral ,  Gert Leusink ,  John William Kostenko ,  Cory Wajda

IPC分类号： H01L21/302

CPC分类号： H01L21/67276 ,  B81C99/0065 ,  B81C2201/0138 ,  H01L21/67253

摘要： A method and system for monitoring status of a system component during a process. The method includes exposing a system component to a reactant gas during a process, where the reactant gas is capable of etching the system component material to form an erosion product, and monitoring release of the erosion product during the process to determine status of the system component. Processes that can be monitored include a chamber cleaning process, a chamber conditioning process, a substrate etching process, and a substrate film formation process. The system component can be a consumable system part such as a process tube, a shield, a ring, a baffle, an injector, a substrate holder, a liner, a pedestal, a cap cover, an electrode, and a heater, any of which can further include a protective coating. The processing system includes the system component in a process chamber, a gas injection system for introducing the reactant gas, a chamber protection system for monitoring the status of the system component, and a controller for controlling the processing system in response to the status.

摘要翻译： 一种在过程中监视系统组件的状态的方法和系统。 该方法包括在过程期间将系统组分暴露于反应气体，其中反应气体能够蚀刻系统组分材料以形成侵蚀产物，并且在该过程期间监测侵蚀产物的释放以确定系统部件的状态 。 可以监测的方法包括室清洁过程，室调节过程，基板蚀刻工艺和基板成膜工艺。 系统组件可以是消耗系统部件，例如处理管，屏蔽件，环，挡板，注射器，衬底保持器，衬垫，基座，帽盖，电极和加热器 其可以进一步包括保护涂层。 处理系统包括处理室中的系统部件，用于引入反应气体的气体注入系统，用于监视系统部件的状态的室保护系统以及响应于状态来控制处理系统的控制器。

公开(公告)号：US06362071B1

公开(公告)日：2002-03-26

申请号：US09542706

申请日：2000-04-05

申请人： Bich-Yen Nguyen ,  William J. Taylor, Jr. ,  Philip J. Tobin ,  David L. O'Meara ,  Percy V. Gilbert ,  Yeong-Jyh T. Lii ,  Victor S. Wang

发明人： Bich-Yen Nguyen ,  William J. Taylor, Jr. ,  Philip J. Tobin ,  David L. O'Meara ,  Percy V. Gilbert ,  Yeong-Jyh T. Lii ,  Victor S. Wang

IPC分类号： H01L2176

CPC分类号： H01L21/76232 ,  H01L21/823481

摘要： In accordance with one embodiment of the present invention, a method is disclosed for forming a semiconductor device having an isolation region (601). A dielectric layer (108) is deposited and etched to form isolation regions (102, 605) having top portions that are narrower than their bottom portions, thereby a tapered isolation region is formed. Active regions (601, 603) are formed using an epitaxial process in the regions between the isolation regions. The resulting active regions (601, 603) have a greater amount of surface area near a top portion, than near a bottom portion. Transistors (721, 723) having opposite polarities are formed within the active areas.

摘要翻译： 根据本发明的一个实施例，公开了一种用于形成具有隔离区域（601）的半导体器件的方法。 沉积和蚀刻电介质层（108）以形成具有比其底部部分更窄的顶部部分的隔离区域（102,605），从而形成锥形隔离区域。 在隔离区域之间的区域中使用外延工艺形成有源区（601,603）。 所得活性区域（601,603）在顶部附近具有比在底部附近更大的表面积。 在有源区域内形成具有相反极性的晶体管（721,723）。

公开(公告)号：US06320784B1

公开(公告)日：2001-11-20

申请号：US09524916

申请日：2000-03-14

申请人： Ramachandran Muralidhar ,  Sucharita Madhukar ,  Bo Jiang ,  Bruce E. White ,  Srikanth B. Samavedam ,  David L. O'Meara ,  Michael Alan Sadd

发明人： Ramachandran Muralidhar ,  Sucharita Madhukar ,  Bo Jiang ,  Bruce E. White ,  Srikanth B. Samavedam ,  David L. O'Meara ,  Michael Alan Sadd

IPC分类号： G11C1100

CPC分类号： B82Y10/00 ,  G11C11/56 ,  G11C11/5671 ,  G11C16/0416 ,  G11C2216/08 ,  H01L29/7887 ,  H01L29/7888

摘要： A memory cell (101), its method of formation, and operation are disclosed. In accordance with one embodiment, the memory cell (101) comprises a first and second current carrying electrode (12) a control electrode (19), and doped discontinuous storage elements (17). In accordance with an alternative embodiment, memory cell programming is accomplished by removing or adding an average of approximately at least a first charge (30, 62, 64), which can be electron(s) or hole(s) from each of the doped discontinuous storage elements (17).

摘要翻译： 公开了一种存储单元（101），其形成方法和操作。 根据一个实施例，存储单元（101）包括第一和第二载流电极（12），控制电极（19）和掺杂的非连续存储元件（17）。 根据替代实施例，存储器单元编程通过去除或添加大约至少第一电荷（30,62,64）的平均值来实现，所述第一电荷可以是来自掺杂的每一个的电子或空穴 不连续存储元件（17）。

公开(公告)号：US5013690A

公开(公告)日：1991-05-07

申请号：US473546

申请日：1990-02-01

申请人： Arthur K. Hochberg ,  David L. O'Meara ,  David A. Roberts

发明人： Arthur K. Hochberg ,  David L. O'Meara ,  David A. Roberts

IPC分类号： H01L21/205 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318

CPC分类号： H01L21/3185 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3145 ,  H01L21/31612 ,  Y10S148/122 ,  Y10S438/934

摘要： A low temperature chemical vapor deposition process comprising heating in a chemical vapor depositon reactor a substrate upon which deposition is desired to a temperature of from about 550.degree. C. to about 750.degree. C. in a chemical vapor deposition reactor having a pressure of from about 0.1 torr to approximately atmospheric pressure, introducing into the reactor a silicon-containing feed and optionally an oxygen containing feed, said silicon containing feed consisting essentially of one or more compounds having the general formula ##STR1## wherein: R.sub.1, R.sub.2, R.sub.3 and R.sub.4 are hydrogen, azido or C-2 to C-6 alkyl, aryl or C-7 to C-10 aralkyl groups, at least one but not more than three of R.sub.1, R.sub.2, R.sub.3 and R.sub.4, being azido, and maintaining the temperature and pressure to cause a film of silicon nitride, silicon oxynitride or silicon dioxide to deposit is disclosed.

摘要翻译： 一种低温化学气相沉积方法，其包括在化学气相沉积反应器中加热基底，在基底上沉积希望在约550℃至约750℃的温度下在具有约 0.1托至约大气压，将含硅进料和任选的含氧进料引入反应器中，所述含硅进料基本上由一种或多种具有通式为其中的化合物组成：其中：R1，R2，R3和R4 是氢，叠氮基或C-2至C-6烷基，芳基或C-7至C-10芳烷基，R1，R2，R3和R4中至少一个但不多于三个为叠氮基，并保持温度 并且公开了使氮化硅，氮氧化硅或二氧化硅的膜沉积的压力。

公开(公告)号：US08460945B2

公开(公告)日：2013-06-11

申请号：US10673513

申请日：2003-09-30

申请人： David L. O'Meara ,  Daniel Craig Burdett ,  Stephen H. Cabral ,  Gert Leusink ,  John William Kostenko ,  Cory Wajda

发明人： David L. O'Meara ,  Daniel Craig Burdett ,  Stephen H. Cabral ,  Gert Leusink ,  John William Kostenko ,  Cory Wajda

IPC分类号： H01L21/00

CPC分类号： H01J37/32935 ,  G01N21/55 ,  G01N21/59

摘要： A method and system are provided for monitoring status of a system component in a process chamber of a batch type processing system. The method includes exposing a system component to light from a light source and monitoring interaction of the light with the system component to determine status of the system component. The method can detect light transmission and/or light reflection from a system component during a process that can include a chamber cleaning process, a chamber conditioning process, a substrate etching process, and a substrate film formation process. The system component can be a consumable system part such as a process tube, a shield, a ring, a baffle, and a liner, and can further contain a protective coating.

摘要翻译： 提供了一种用于监视批处理系统的处理室中的系统组件的状态的方法和系统。 该方法包括将系统组件暴露于来自光源的光并监测光与系统组件的相互作用以确定系统组件的状态。 该方法可以在可以包括室清洁过程，室调节过程，基板蚀刻工艺和基板成膜工艺的过程中检测来自系统部件的光透射和/或光反射。 系统组件可以是消耗系统部件，例如处理管，屏蔽，环，挡板和衬垫，并且还可以包含保护涂层。

公开(公告)号：US07509962B2

公开(公告)日：2009-03-31

申请号：US11038129

申请日：2005-01-21

申请人： David L. O'Meara ,  Shingo Maku

发明人： David L. O'Meara ,  Shingo Maku

IPC分类号： B08B6/00

CPC分类号： C03C17/001 ,  C03C17/22 ,  C03C17/23 ,  C03C2217/228 ,  C03C2217/258 ,  C03C2218/31 ,  C03C2218/33 ,  C23C16/4405 ,  Y10S438/905

摘要： A method and control system for treating a hafnium-based dielectric processing system in which a system component of the processing system is exposed to a chlorine-containing gas. A residual hafnium by-product remaining in the processing system after a hafnium removal process is reacted with a chlorine-containing etchant derived from the chlorine-containing gas. A chlorinated hafnium product is volatilized for exhaustion from the processing system. The control system can utilize a computer readable medium to introduce a chlorine-containing gas to the processing system, to adjust at least one of a temperature and a pressure in the processing system to produce from the chlorine-containing gas a chlorine-containing etchant for dissolution of a residual hafnium by-product remaining in the processing system after a hafnium silicate, hafnium oxide, or hafnium oxynitride removal process, and to exhaust a chlorinated hafnium product from the processing system.

摘要翻译： 一种用于处理其中处理系统的系统组件暴露于含氯气体的铪基介质处理系统的方法和控制系统。 在除去铪之后残留在处理系统中的残余铪副产物与来自含氯气体的含氯蚀刻剂反应。 氯化铪产品从处理系统中挥发以用尽。 控制系统可利用计算机可读介质向处理系统引入含氯气体，以调节处理系统中的温度和压力中的至少一个，以从含氯气体中产生含氯气体的含氯蚀刻剂 在硅酸铪，氧化铪或氮氧化铪去除工艺之后残留在处理系统中的残余铪副产物的溶解，并从处理系统中排出氯化铪产物。

公开(公告)号：US06686633B1

公开(公告)日：2004-02-03

申请号：US09653338

申请日：2000-08-31

申请人： Craig S. Lage ,  Mousumi Bhat ,  Yeong-Jyh Tom Lii ,  Andrew G. Nagy ,  Larry E. Frisa ,  Stanley M. Filipiak ,  David L. O'Meara ,  T. P. Ong ,  Michael P. Woo ,  Terry G. Sparks ,  Carol M. Gelatos

发明人： Craig S. Lage ,  Mousumi Bhat ,  Yeong-Jyh Tom Lii ,  Andrew G. Nagy ,  Larry E. Frisa ,  Stanley M. Filipiak ,  David L. O'Meara ,  T. P. Ong ,  Michael P. Woo ,  Terry G. Sparks ,  Carol M. Gelatos

IPC分类号： H01L2976

CPC分类号： H01L27/11 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/1104

摘要： A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.

摘要翻译： 半导体器件包括静态随机存取存储器单元的存储器阵列。 使用与逻辑型器件更紧密相关联的工艺流程来形成SRAM单元。 SRAM单元使用一个半导体层形成，与至少三个SRAM单元相似。 SRAM单元包括许多特征，允许其尺寸缩放到非常小的尺寸（小于0.25微米，并且可能低至0.1微米甚至更小）。 独特的过程集成方案允许形成局部互连（522和524），其中每个局部互连（522,524）交叉耦合SRAM的反相器并形成在单个开口（70）内。 此外，字线的互连部分（104）横向偏离同一字线的硅部分（36），使得互连部分不干扰位线连接。