公开(公告)号：US08841969B2

公开(公告)日：2014-09-23

申请号：US13670016

申请日：2012-11-06

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sang-Heung Lee ,  Seong-Il Kim ,  Dong Min Kang ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Chull Won Ju ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H03G3/12

CPC classification number: H03G1/0082 ,  H03G1/0088 ,  H03G3/3084

Abstract: Disclosed is an automatic gain control feedback amplifier that can arbitrarily control a gain even when a difference in input signal is large. The automatic gain control feedback amplifier includes: an amplification circuit unit configured to amplify voltage input from an input terminal and output the amplified voltage to an output terminal; a feedback circuit unit connected between the input terminal and the output terminal and including a feedback resistor unit of which a total resistance value is determined by one or more control signals and a feedback transistor connected to the feedback resistor unit in parallel; and a bias circuit unit configured to supply predetermined bias voltage to the feedback transistor.

Abstract translation: 公开了一种自动增益控制反馈放大器，其即使当输入信号的差异大时也可以任意地控制增益。 自动增益控制反馈放大器包括：放大电路单元，被配置为放大从输入端输入的电压，并将放大的电压输出到输出端; 连接在输入端子和输出端子之间的反馈电路单元，包括反馈电阻器单元，其总电阻值由一个或多个控制信号确定，反馈晶体管并联连接到反馈电阻器单元; 以及偏置电路单元，被配置为向所述反馈晶体管提供预定的偏置电压。

公开(公告)号：US20140160689A1

公开(公告)日：2014-06-12

申请号：US13959666

申请日：2013-08-05

Applicant: Electronics and Telecommunications Research Institute

Inventor： Dong Min KANG ,  Chull Won Ju ,  Seong-Il Kim ,  Sang-Heung Lee ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H05K1/02

CPC classification number: H01L23/66 ,  H01L23/49844 ,  H01L2223/6655 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A package includes a ground plate, a chip mounting plate disposed at a side of the ground plate and having a top surface lower than a top surface of the ground plate, a chip on the chip mounting plate, a first input/output terminal opposite to the chip mounting plate and disposed at another side of the ground plate, and a second input/output terminal opposite to the ground plate and disposed at a side of the chip mounting plate. The first and second input/output terminals are electrically connected to the chip.

Abstract translation: 一种封装，包括接地板，设置在接地板一侧的芯片安装板，具有比接地板的顶表面低的顶表面，芯片安装板上的芯片，与第一输入/输出端子相对的第一输入/输出端子 芯片安装板并且设置在接地板的另一侧，以及与接地板相对的第二输入/输出端子，并且设置在芯片安装板的一侧。 第一和第二输入/输出端子与芯片电连接。

公开(公告)号：US10608102B2

公开(公告)日：2020-03-31

申请号：US16137235

申请日：2018-09-20

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Hokyun Ahn ,  Min Jeong Shin ,  Jeong Jin Kim ,  Hae Cheon Kim ,  Jae Won Do ,  Byoung-Gue Min ,  Hyung Sup Yoon ,  Hyung Seok Lee ,  Jong-Won Lim ,  Sungjae Chang ,  Hyunwook Jung ,  Kyu Jun Cho ,  Dong Min Kang ,  Dong-Young Kim ,  Seong-Il Kim ,  Sang-Heung Lee ,  Jongmin Lee ,  Hong Gu Ji

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/778 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/417 ,  H01L29/06 ,  H01L29/20 ,  H01L29/423

Abstract: Provided is a semiconductor device including a substrate in which an insulation layer is disposed between a first semiconductor layer and a second semiconductor layer, a through-hole penetrating through the substrate, the through-hole having a first hole penetrating through the first semiconductor layer and a second hole penetrating through the insulation layer and the second semiconductor layer from a bottom surface of the first hole, an epi-layer disposed inside the through-hole, a drain electrode disposed inside the second hole and contacting one surface of the epi-layer, and a source electrode and a gate electrode which are disposed on the other surface of the epi-layer.

公开(公告)号：US10256811B2

公开(公告)日：2019-04-09

申请号：US15654792

申请日：2017-07-20

Applicant: Electronics and Telecommunications Research Institute

Inventor： Woojin Chang ,  Jong-Won Lim ,  Dong Min Kang ,  Dong-Young Kim ,  Seong-il Kim ,  Hae Cheon Kim ,  Jae Won Do ,  Byoung-Gue Min ,  Min Jeong Shin ,  Hokyun Ahn ,  Hyung Sup Yoon ,  Sang-Heung Lee ,  Jongmin Lee ,  Sungjae Chang ,  Yoo Jin Jang ,  Hyunwook Jung ,  Kyu Jun Cho ,  Hong Gu Ji

IPC: H03K17/687 ,  H03K17/693 ,  G11C5/14 ,  H03K19/0175 ,  H03K3/353 ,  H03K17/0812 ,  H03K17/10 ,  H03K17/12 ,  H03K17/14 ,  H03K17/16 ,  H03K17/28

Abstract: Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.

公开(公告)号：US09224830B2

公开(公告)日：2015-12-29

申请号：US13914713

申请日：2013-06-11

Applicant: Electronics and Telecommunications Research Institute

Inventor： Seong-Il Kim ,  Jong-Won Lim ,  Dong Min Kang ,  Sang-Heung Lee ,  Hyung Sup Yoon ,  Chull Won Ju ,  Byoung-Gue Min ,  Jongmin Lee ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H01L29/812 ,  H01L29/66 ,  H01L29/40 ,  H01L29/41 ,  H01L29/423 ,  H01L29/778 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/66477 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/40 ,  H01L29/401 ,  H01L29/402 ,  H01L29/41 ,  H01L29/42312 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/812

Abstract: A field effect transistor is provided. The transistor may include a source electrode and a drain electrode provided spaced apart from each other on a substrate and a ‘+’-shaped gate electrode provided on a portion of the substrate located between the source and drain electrodes.

Abstract translation: 提供场效应晶体管。 晶体管可以包括在基板上彼此间隔开设置的源电极和漏电极，以及设置在位于源极和漏极之间的基板的一部分上的“+”形栅电极。

公开(公告)号：US08901608B2

公开(公告)日：2014-12-02

申请号：US13908076

申请日：2013-06-03

Applicant: Electronics and Telecommunications Research Institute

Inventor： Jong-Won Lim ,  Hokyun Ahn ,  Woojin Chang ,  Dong Min Kang ,  Seong-Il Kim ,  Sang-Heung Lee ,  Hyung Sup Yoon ,  Chull Won Ju ,  Hae Cheon Kim ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H01L33/00 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/778 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66431

Abstract: A high electron mobility transistor includes a T-type gate electrode disposed on a substrate between source and drain electrodes and insulating layers disposed between the substrate and the T-type gate electrode. The insulating layers include first, second, and third insulating layers. The third insulating layer is disposed between the substrate and a head portion of the T-type gate electrode such that a portion of the third insulating layer is in contact with a foot portion of the T-type gate electrode. The second insulating layer is disposed between the substrate and the head portion of the T-type gate electrode to be in contact with the third insulating layer. The first insulating layer and another portion of the third insulating layer are sequentially stacked between the substrate and the head portion of the T-type gate electrode to be in contact with the second insulating layer.

Abstract translation: 高电子迁移率晶体管包括设置在源极和漏极之间的衬底上的T型栅电极和设置在衬底和T型栅电极之间的绝缘层。 绝缘层包括第一绝缘层，第二绝缘层和第三绝缘层。 第三绝缘层设置在基板和T型栅电极的头部之间，使得第三绝缘层的一部分与T型栅极的脚部接触。 第二绝缘层设置在基板与T型栅电极的头部之间以与第三绝缘层接触。 所述第一绝缘层和所述第三绝缘层的另一部分依次层叠在所述基板与所述T型栅电极的头部之间，以与所述第二绝缘层接触。