公开(公告)号：US06902966B2

公开(公告)日：2005-06-07

申请号：US09983625

申请日：2001-10-25

Applicant: Bin Yu ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Qi Xiang

Inventor： Bin Yu ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Qi Xiang

IPC: H01L21/28 ,  H01L21/20 ,  H01L21/265 ,  H01L21/268 ,  H01L21/336 ,  H01L29/417 ,  H01L29/78 ,  H01L21/00

CPC classification number: H01L29/665 ,  H01L21/268

Abstract: A method of manufacturing a MOSFET semiconductor device comprises forming a gate electrode over a substrate and a gate oxide between the gate electrode and the substrate; forming source/drain extensions in the substrate; forming first and second sidewall spacers; implanting dopants within the substrate to form source/drain regions in the substrate adjacent to the sidewalls spacers; laser thermal annealing to activate the source/drain regions; depositing a layer of nickel over the source/drain regions; and annealing to form a nickel silicide layer disposed on the source/drain regions. The source/drain extensions and sidewall spacers are adjacent to the gate electrode. The source/drain extensions can have a depth of about 50 to 300 angstroms, and the source/drain regions can have a depth of about 400 to 1000 angstroms. The annealing is at temperatures from about 350 to 500° C.

Abstract translation: 一种制造MOSFET半导体器件的方法包括：在栅极电极和衬底之间形成衬底上的栅电极和栅极氧化物; 在衬底中形成源极/漏极延伸部; 形成第一和第二侧壁间隔物; 在所述衬底内注入掺杂剂以在所述衬底中邻近所述侧壁间隔物形成源/漏区; 激光热退火激活源/漏区; 在源极/漏极区域上沉积镍层; 并退火以形成设置在源/漏区上的硅化镍层。 源极/漏极延伸部和侧壁间隔物与栅电极相邻。 源极/漏极延伸部可以具有约50至300埃的深度，并且源极/漏极区域可以具有约400至1000埃的深度。 退火温度在约350-500℃

公开(公告)号：US06867080B1

公开(公告)日：2005-03-15

申请号：US10460165

申请日：2003-06-13

Applicant: Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

Inventor： Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

IPC: H01L21/20 ,  H01L21/268 ,  H01L21/28 ,  H01L21/321 ,  H01L21/8234 ,  H01L21/338 ,  H01L21/331 ,  H01L21/94

CPC classification number: H01L21/28176 ,  H01L21/2026 ,  H01L21/268 ,  H01L21/28035 ,  H01L21/321 ,  H01L21/823437 ,  Y10S438/926

Abstract: A method is provided for eliminating uneven heating of substrate active areas during laser thermal annealing (LTA) due to variations in gate electrode density. Embodiments include adding dummy structures, formed simultaneously with the gate electrodes, to “fill in” the spaces between isolated gate electrodes, such that the spacing between the gate electrodes and the dummy structures is the same as the spacing between the densest array of device structures on the substrate surface. Since the surface features (i.e., the gate electrodes and the dummy structures) appear substantially uniform to the LTA laser, the laser radiation is uniformly absorbed by the substrate, and the substrate surface is evenly heated.

Abstract translation: 提供了一种用于消除激光热退火（LTA）期间基板有源区的不均匀加热的方法，这是由于栅电极密度的变化。 实施例包括添加与栅电极同时形成的虚拟结构以“填充”隔离栅电极之间的空间，使得栅电极和虚拟结构之间的间隔与器件结构最密集阵列之间的间隔相同 在基板表面上。 由于表面特征（即，栅电极和虚拟结构）对于LTA激光器而言基本上均匀，激光辐射被基板均匀地吸收，并且基板表面被均匀地加热。

公开(公告)号：US06825115B1

公开(公告)日：2004-11-30

申请号：US10341436

申请日：2003-01-14

Applicant: Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

Inventor： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

IPC: H01L2144

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/28518 ,  H01L29/665

Abstract: Dopant deactivation, particularly at the Si/silicide interface, is avoided by forming deep source/drain implants after forming silicide layers on the substrate and activating the source/drain regions by laser thermal annealing. Embodiments include forming source/drain extensions, forming metal silicide layers on the substrate surface and gate electrode, forming preamorphized regions under the metal silicide layers in the substrate, ion implanting to form deep source/drain implants overlapping the preamorphized regions and extending deeper into the substrate then the preamorphized regions, and laser thermal annealing to activate the deep source/drain regions.

Abstract translation: 通过在衬底上形成硅化物层并通过激光热退火来激活源极/漏极区域之后形成深源极/漏极注入来避免掺杂失活，特别是Si /硅化物界面。 实施例包括形成源极/漏极延伸部，在衬底表面上形成金属硅化物层和栅电极，在衬底中的金属硅化物层下方形成预变形区域;离子注入，以形成与预变形区域重叠的深源/漏植入物， 衬底然后是前变形区域，激光热退火激活深源/漏区。

公开(公告)号：US06746944B1

公开(公告)日：2004-06-08

申请号：US10341345

申请日：2003-01-14

Applicant: Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

Inventor： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

IPC: H01L213205

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/7833

Abstract: Semiconductor devices with reduced NiSi/Si interface contact resistance are fabricated by forming preamorphized regions in a substrate at a depth overlapping the subsequently formed NiSi/Si interface, ion implanting impurities to form deep source/drain implants overlapping the preamorphized regions deeper in the substrate and laser thermal annealing to activate the deep source/drain regions. Nickel silicide layers are then formed in a main surface of the substrate and on the gate electrode. Embodiments include forming deep source/drain regions with an activated impurity concentration of 1×1020 to 1×1021 atoms/cm3 at the NiSi/Si interface.

Abstract translation: 具有降低的NiSi / Si界面接触电阻的半导体器件通过在与随后形成的NiSi / Si界面重叠的深度的衬底中形成预变形区域，离子注入杂质以形成与衬底中较深的预变形区域重叠的深源/漏注入; 激光热退火激活深源/漏区。 然后在衬底的主表面和栅电极上形成硅化镍层。 实施例包括在NiSi / Si界面处形成具有1×10 20至1×10 21原子/ cm 3的活化杂质浓度的深源/漏区。

公开(公告)号：US06682973B1

公开(公告)日：2004-01-27

申请号：US10147650

申请日：2002-05-16

Applicant: Eric N. Paton ,  Qi Xiang ,  Bin Yu

Inventor： Eric N. Paton ,  Qi Xiang ,  Bin Yu

IPC: H01L218242

CPC classification number: H01L21/28185 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02249 ,  H01L21/02255 ,  H01L21/2807 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28291 ,  H01L21/31604 ,  H01L21/31662 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A process for fabricating a semiconductor device having a high-K dielectric layer over a silicon substrate, including steps of growing on the silicon substrate an interfacial layer of a silicon-containing dielectric material; and depositing on the interfacial layer a layer comprising at least one high-K dielectric material, in which the interfacial layer is grown by laser excitation of the silicon substrate in the presence of oxygen, nitrous oxide, nitric oxide, ammonia or a mixture of two or more thereof. In one embodiment, the silicon-containing material is silicon dioxide, silicon nitride, silicon oxynitride or a mixture thereof.

Abstract translation: 一种用于制造在硅衬底上具有高K电介质层的半导体器件的方法，包括在硅衬底上生长含硅介电材料的界面层的步骤; 并且在所述界面层上沉积包含至少一种高K电介质材料的层，其中所述界面层通过在氧，一氧化二氮，一氧化氮，氨或两者的混合物的存在下通过硅衬底的激光激发而生长 或更多。 在一个实施方案中，含硅材料是二氧化硅，氮化硅，氮氧化硅或其混合物。

公开(公告)号：US06555439B1

公开(公告)日：2003-04-29

申请号：US10021551

申请日：2001-12-18

Applicant: Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

Inventor： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

IPC: H01L2100

CPC classification number: H01L21/324 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/28176 ,  H01L21/28211 ,  H01L29/6659

Abstract: A method of manufacturing a MOSFET semiconductor device includes forming a gate electrode over a substrate and a gate oxide between the gate electrode and the substrate, forming source/drain extensions in the substrate, and forming first and second sidewall spacers. Dopants are then implanted within the substrate to form amorphitized source/drain regions in the substrate adjacent to the sidewalls spacers. The amorphitized source/drain regions are partially recrystallized, and laser thermal annealing activates the source/drain regions. The source/drain extensions and sidewall spacers are adjacent to the gate electrode. The source/drain extensions can have a depth of about 50 to 300 angstroms, and the source/drain regions can have a depth of about 400 to 1000 angstroms. Also, the recrystallization reduces the amorphitized source/drain regions by a depth of about 20 to 100 angstroms. A semiconductor device is also disclosed.

Abstract translation: 一种制造MOSFET半导体器件的方法包括在衬底上形成栅电极和在栅电极和衬底之间形成栅极氧化物，在衬底中形成源极/漏极延伸部分，以及形成第一和第二侧壁间隔物。 然后将掺杂剂注入到衬底内以在邻近侧壁间隔物的衬底中形成非晶化的源极/漏极区。 非晶化的源极/漏极区域被部分再结晶，并且激光热退火激活源极/漏极区域。 源极/漏极延伸部和侧壁间隔物与栅电极相邻。 源极/漏极延伸部可以具有约50至300埃的深度，并且源极/漏极区域可以具有约400至1000埃的深度。 此外，重结晶将非晶化的源/漏区减少约20至100埃的深度。 还公开了一种半导体器件。

公开(公告)号：US06551888B1

公开(公告)日：2003-04-22

申请号：US10020496

申请日：2001-12-18

Applicant: Cyrus E. Tabery ,  Eric N. Paton ,  Bin Yu ,  Qi Xiang ,  Robert B. Ogle

Inventor： Cyrus E. Tabery ,  Eric N. Paton ,  Bin Yu ,  Qi Xiang ,  Robert B. Ogle

IPC: H01L21336

CPC classification number: H01L21/268 ,  H01L21/2026 ,  H01L29/6659

Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode over a substrate, introducing dopants into the substrate, forming a tuning layer over at least a portion of the substrate, and activating the dopants using laser thermal annealing. The tuning layer causes an increase or a decrease in the amount of fluence absorbed by the portion of substrate below the tuning layer in comparison to an amount of fluence absorbed by a portion of substrate not covered by the tuning layer. Additional tuning layers can also be formed over the substrate.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成栅电极，将掺杂剂引入衬底中，在衬底的至少一部分上形成调谐层，并使用激光热退火激活掺杂剂。 与由调谐层未被覆盖的基板的一部分吸收的注量相比，调谐层引起由调谐层下方的基板部分吸收的注量的增加或减少。 也可以在衬底上形成附加的调谐层。

公开(公告)号：US07402485B1

公开(公告)日：2008-07-22

申请号：US11229864

申请日：2005-09-19

Applicant: William G. En ,  Thorsten Kammler ,  Eric N. Paton ,  Scott D. Luning

Inventor： William G. En ,  Thorsten Kammler ,  Eric N. Paton ,  Scott D. Luning

IPC: H01L21/8238

CPC classification number: H01L29/6656 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subsequent cleaning process. An epitaxial layer is formed subsequent to the cleaning process.

Abstract translation: 侧壁间隔结构邻近门结构形成，由此形成侧壁间隔结构的外表面的材料含有氮。 在其形成之后，侧壁间隔结构被退火以使后壁清洁过程的侧壁间隔结构硬化。 在清洁处理之后形成外延层。

公开(公告)号：US06787864B2

公开(公告)日：2004-09-07

申请号：US10335492

申请日：2002-12-31

Applicant: Eric N. Paton ,  Qi Xiang ,  Paul R. Besser ,  Ming-Ren Lin ,  Minh V. Ngo ,  Haihong Wang

Inventor： Eric N. Paton ,  Qi Xiang ,  Paul R. Besser ,  Ming-Ren Lin ,  Minh V. Ngo ,  Haihong Wang

IPC: H01L2972

CPC classification number: H01L29/4933 ,  H01L21/28052 ,  H01L29/1054 ,  H01L29/4908 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A MOSFET gate or a MOSFET source or drain region comprises silicon germanium or polycrystalline silicon germanium. Silicidation with nickel is performed to form a nickel germanosilicide that preferably comprises the monosilicide phase of nickel silicide. The inclusion of germanium in the silicide provides a wider temperature range within which the monosilicide phase may be formed, while essentially preserving the superior sheet resistance exhibited by nickel monosilicide. As a result, the nickel germanosilicide is capable of withstanding greater temperatures during subsequent processing than nickel monosilicide, yet provides approximately the same sheet resistance and other beneficial properties as nickel monosilicide.

公开(公告)号：US06559051B1

公开(公告)日：2003-05-06

申请号：US09679881

申请日：2000-10-05

Applicant: Matthew S. Buynoski ,  Paul R. Besser ,  Paul L. King ,  Eric N. Paton ,  Qi Xang

Inventor： Matthew S. Buynoski ,  Paul R. Besser ,  Paul L. King ,  Eric N. Paton ,  Qi Xang

IPC: H01L2144

CPC classification number: H01L21/28194 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66583

Abstract: High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are formed by electrolessly plating a metal or metal-based dielectric precursor layer comprising at least one refractory or lanthanum series transition metal, such as of Zr and/or Hf, on a silicon-based semiconductor substrate and then reacting the precursor layer with oxygen or with oxygen and the Si-based semiconductor substrate to form the at least one metal oxide or silicate. The inventive methodology prevents, or at least substantially reduces, oxygen access to the substrate surface during at least the initial stage(s) of formation of the gate insulator layer, thereby minimizing deleterious formation of oxygen-induced surface states at the semiconductor substrate/gate insulator interface.

Abstract translation: 通过无电镀法形成高质量电介质层，例如由至少一种耐火材料或镧系列过渡金属氧化物或硅酸盐构成的高k电介质层，用作叠层金属栅极MOS晶体管和CMOS器件中的栅极绝缘体层 金属或金属基电介质前体层，其在硅基半导体衬底上包含至少一种难熔或镧系过渡金属，例如Zr和/或Hf，然后使前体层与氧或氧与Si反应 的半导体衬底以形成至少一种金属氧化物或硅酸盐。 本发明的方法在至少形成栅极绝缘体层的初始阶段期间防止或至少基本上减少氧接触到衬底表面，从而最小化半导体衬底/栅极处的氧诱导表面状态的有害形成 绝缘子接口。