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    SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE WITH SELECTIVELY PLACED SUB-INSULATOR LAYER VOID(S) AND METHOD OF FORMING THE SOI STRUCTURE
    12.
    发明申请
    SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE WITH SELECTIVELY PLACED SUB-INSULATOR LAYER VOID(S) AND METHOD OF FORMING THE SOI STRUCTURE 有权
    具有选择性的绝缘子层绝缘体的半导体绝缘体（SOI）结构和形成SOI结构的方法

    公开(公告)号：US20120018806A1

    公开(公告)日：2012-01-26

    申请号：US12842146

    申请日：2010-07-23

    申请人： Toshiharu Furukawa ,  Robert R. Robison ,  Richard Q. Williams

    发明人： Toshiharu Furukawa ,  Robert R. Robison ,  Richard Q. Williams

    IPC分类号： H01L27/12 ,  H01L21/84

    CPC分类号： H01L29/66477 ,  H01L21/02104 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78648 ,  H01L29/78654

    摘要： Disclosed is a semiconductor-on-insulator (SOI) structure having sub-insulator layer void(s) selectively placed in a substrate so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling between a second section of the semiconductor layer and the substrate. The first section may contain a first device on an insulator layer and the second section may contain a second device on the insulator layer. Alternatively, the first and second sections may comprise different regions of the same device on an insulator layer. For example, in an SOI field effect transistor (FET), sub-insulator layer voids can be selectively placed in the substrate below the source, drain and/or body contact diffusion regions, but not below the channel region so that capacitance coupling between the these various diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate. Also, disclosed is an associated method of forming such an SOI structure.

    摘要翻译： 公开了一种绝缘体半导体（SOI）结构，其具有选择性地放置在衬底中的次绝缘体层空穴，使得半导体层的第一部分与衬底之间的电容耦合将小于第二 半导体层和衬底的截面。 第一部分可以包含绝缘体层上的第一器件，第二部分可以在绝缘体层上包含第二器件。 或者，第一和第二部分可以包括绝缘体层上相同器件的不同区域。 例如，在SOI场效应晶体管（FET）中，可以将子绝缘体层空隙选择性地放置在源极，漏极和/或体接触扩散区域下方的衬底中，但不能在沟道区域下方，使得电容耦合 这些各种扩散区域和衬底将小于沟道区域和衬底之间的电容耦合。 此外，公开了形成这种SOI结构的相关方法。

    Band gap modulated optical sensor
    14.
    发明授权
    Band gap modulated optical sensor 有权
    带隙调制光传感器

    公开(公告)号：US08008696B2

    公开(公告)日：2011-08-30

    申请号：US12146575

    申请日：2008-06-26

    申请人： Kangguo Cheng ,  Toshiharu Furukawa ,  Robert Robison ,  William R. Tonti

    发明人： Kangguo Cheng ,  Toshiharu Furukawa ,  Robert Robison ,  William R. Tonti

    IPC分类号： H01L29/72

    CPC分类号： H01L27/14645 ,  H01L27/14627

    摘要： A complementary metal-oxide-semiconductor (CMOS) optical sensor structure comprises a pixel containing a charge collection well of a same semiconductor material as a semiconductor layer in a semiconductor substrate and at least another pixel containing another charge collection well of a different semiconductor material than the material of the semiconductor layer. The charge collections wells have different band gaps, and consequently, generate charge carriers in response to light having different wavelengths. The CMOS sensor structure thus includes at least two pixels responding to light of different wavelengths, enabling wavelength-sensitive, or color-sensitive, capture of an optical data. Further, a design structure for the inventive complementary metal-oxide-semiconductor (CMOS) image sensor is also provided.

    摘要翻译： 互补金属氧化物半导体（CMOS）光学传感器结构包括含有与半导体衬底中的半导体层相同的半导体材料的电荷收集阱的像素，以及包含不同半导体材料的另一电荷收集阱的至少另一个像素 半导体层的材料。 电荷收集阱具有不同的带隙，因此响应于具有不同波长的光而产生电荷载流子。 因此，CMOS传感器结构包括响应于不同波长的光的至少两个像素，使得能够对光学数据进行波长敏感或颜色敏感的捕获。 此外，还提供了本发明的互补金属氧化物半导体（CMOS）图像传感器的设计结构。

    Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (S0I) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor
    16.
    发明授权
    Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (S0I) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor 有权
    在绝缘体上硅（S0I）晶片上形成具有嵌入式和多面源极/漏极应力的平面场效应晶体管的方法，平面场效应晶体管结构和用于平面场效应晶体管的设计结构

    公开(公告)号：US07951657B2

    公开(公告)日：2011-05-31

    申请号：US12470001

    申请日：2009-05-21

    申请人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  Toshiharu Furukawa ,  Xuefeng Hua

    发明人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  Toshiharu Furukawa ,  Xuefeng Hua

    IPC分类号： H01L21/84

    CPC分类号： H01L29/66636 ,  H01L21/26506 ,  H01L29/1079 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78654

    摘要： Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.

    摘要翻译： 公开了一种在SOI晶片上形成具有嵌入和切向的源极/漏极应力源的平面FET的方法的实施例。 该方法包括定向离子注入工艺，以在SOI晶片的单晶半导体层中的源极/漏极凹槽的底表面处产生非晶区域。 然后，可以执行对不同结晶平面在其它晶体上的选择性的蚀刻工艺，并且对非晶半导体材料上的单晶半导体材料进一步选择性的蚀刻工艺，以便选择性地调节凹陷侧壁的形状（即，轮廓）而不增加 凹槽 随后，可以进行退火处理以使非晶区域再结晶，并且可以使用外延沉积工艺来用源极/漏极应力材料填充凹部。 还公开了平面FET结构和平面FET的设计结构的实施例。

    Phase change memory cell with vertical transistor
    19.
    发明授权
    Phase change memory cell with vertical transistor 有权
    具有垂直晶体管的相变存储单元

    公开(公告)号：US07932167B2

    公开(公告)日：2011-04-26

    申请号：US11771457

    申请日：2007-06-29

    申请人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles William Koburger, III ,  Chung Hon Lam

    发明人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles William Koburger, III ,  Chung Hon Lam

    IPC分类号： H01L21/44

    CPC分类号： H01L45/06 ,  G11C13/0004 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1683

    摘要： A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is formed on the lower electrode feature and has one or more sidewalls. It comprises a lower doped feature, a middle doped feature formed above the lower doped feature, and an upper doped feature formed above the middle doped feature. The sacrificial feature is formed above the island, while the gate feature is formed along each sidewall of the island. The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein. Finally, the phase feature is formed above the island at least in part by replacing at least a portion of the sacrificial feature with a phase change material. The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal.

    摘要翻译： 部分地通过形成下电极特征，岛，牺牲特征，栅极特征和相变特征来制造集成电路中的存储单元。 岛形成在下电极特征上并具有一个或多个侧壁。 它包括下掺杂特征，形成在下掺杂特征之上的中掺杂特征，以及形成在中掺杂特征之上的上掺杂特征。 牺牲特征形成在岛上方，而栅极特征沿着岛的每个侧壁形成。 栅极特征覆盖岛的中间掺杂特征的至少一部分，并且可操作以控制其中的电阻。 最后，相位特征至少部分地通过用相变材料代替牺牲特征的至少一部分而在岛上方形成。 响应于电信号的应用，相变材料可操作以在较低和较高的电阻状态之间切换。