公开(公告)号：US20190278166A1

公开(公告)日：2019-09-12

申请号：US15915280

申请日：2018-03-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Sun ,  Guoxiang Ning ,  Lloyd C. Litt

IPC: G03F1/58 ,  H01L21/027 ,  G03F1/64 ,  G03F7/20 ,  G03F1/22

Abstract: Disclosed is a reticle with multiple different sets of redundant mask patterns. Each set allows for patterning of a layer at a specific level of an integrated circuit (IC) chip design on a target region of a wafer using a vote-taking technique to avoid defects. The different sets further allow the same reticle to be used to pattern layers at different levels in the same IC chip design or to pattern layers at the same level or at different levels in different IC chip designs. Each mask pattern is individually framed with alignment marks to facilitate alignment minimize overlay errors. Optionally, redundant mask patterns in the same set are distributed across the reticle (as opposed to being located within the same general area) in order to minimize reticle overheating during patterning using the vote-taking technique. Also disclosed are a photolithography system and a photolithography method that employ such a reticle.

公开(公告)号：US10002827B2

公开(公告)日：2018-06-19

申请号：US15458140

申请日：2017-03-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Yuping Ren ,  Chin Teong Lim ,  Xusheng Wu ,  Paul Ackmann

IPC: G06F17/50 ,  H01L23/522 ,  G03F1/36 ,  H01L23/528

CPC classification number: H01L23/5226 ,  G03F1/36 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0207

Abstract: Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes.

公开(公告)号：US09368453B2

公开(公告)日：2016-06-14

申请号：US14948476

申请日：2015-11-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Chan Seob Cho ,  Paul Ackmann ,  Jung Yu Hsieh ,  Hui Peng Koh

IPC: H01L23/544 ,  H01L29/49

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F7/70683 ,  H01L21/3212 ,  H01L22/12 ,  H01L27/088 ,  H01L29/4916 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming dummy structures and an overlay mark protection zone over an active layer zone based on the shape of an overlay mark and the resulting device are provided. Embodiments include determining a size and a shape of an overlay mark; determining a size and a shape of an overlay mark protection zone based on the shape of the overlay mark; determining a shape of a plurality of dummy structures based on the shape of the overlay mark; determining a size and a shape of an active layer zone based on the size and the shape of the overlay mark and the plurality of dummy structures; forming the active layer zone in an active layer of a semiconductor substrate; forming the overlay mark and the plurality of dummy structures over the active layer zone in a poly layer of the semiconductor substrate; and planarizing the poly layer.

Abstract translation: 提供了基于覆盖标记的形状和所得到的装置在有源层区域上形成虚拟结构和覆盖标记保护区域的方法。 实施例包括确定重叠标记的尺寸和形状; 基于覆盖标记的形状确定覆盖标记保护区的大小和形状; 基于重叠标记的形状确定多个虚拟结构的形状; 基于覆盖标记和多个虚拟结构的尺寸和形状来确定活动层区域的尺寸和形状; 在半导体衬底的有源层中形成有源层区; 在所述半导体衬底的多晶硅层中的所述有源层区域上形成所述覆盖标记和所述多个虚设结构; 并平坦化多层。

公开(公告)号：US09250538B2

公开(公告)日：2016-02-02

申请号：US14146771

申请日：2014-01-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Christopher Spence ,  Paul Ackmann ,  Chin Teong Lim

IPC: G06F17/50 ,  G03F7/20 ,  G03F1/70

CPC classification number: G03F7/70441 ,  G03F1/70 ,  Y02T10/82

Abstract: A method and apparatus for an efficient optical proximity correction (OPC) repair flow is disclosed. Embodiments may include receiving an input data stream of an integrated circuit (IC) design layout, performing one or more iterations of an OPC step and a layout polishing step on the input data stream, and performing a smart enhancement step if an output of a last iteration of the OPC step fails to satisfy one or more layout criteria and if a number of the one or more iterations satisfies a threshold value. Additional embodiments may include performing a pattern insertion process cross-linked with the OPC step, the pattern insertion process being a base optical rule check (ORC) process.

Abstract translation: 公开了一种用于高效光学邻近校正（OPC）修复流程的方法和装置。 实施例可以包括接收集成电路（IC）设计布局的输入数据流，对输入数据流执行OPC步骤的一个或多个迭代和布局抛光步骤，以及如果最后一个输出的输出执行智能增强步骤 OPC步骤的迭代不能满足一个或多个布局标准，并且如果一个或多个迭代的数量满足阈值。 附加实施例可以包括执行与OPC步骤交联的模式插入过程，模式插入过程是基本光学规则检查（ORC）过程。

公开(公告)号：US10923388B2

公开(公告)日：2021-02-16

申请号：US16252114

申请日：2019-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou Huang ,  Yuping Ren ,  Paul Ackmann ,  Guoxiang Ning

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/283 ,  H01L21/311

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gap fill void and connection structures and methods of manufacture. The structure includes: a gate structure comprising source and drain regions; a gate contact in direct contact and overlapping the gate structure; and source and drain contacts directly connecting to the source and drain regions, respectively.

公开(公告)号：US20200118927A1

公开(公告)日：2020-04-16

申请号：US16161590

申请日：2018-10-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiaoqiang Zhang ,  Guoxiang Ning ,  Jiehui Shu

IPC: H01L23/525 ,  H01L21/768

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an anti-fuse with self-aligned via patterning and methods of manufacture. The anti-fuse includes: a lower wiring layer composed of a plurality of lower wiring structures; at least one via structure in direct contact and misaligned with a first wiring structure of the plurality of lower wiring structures and offset from a second wiring structure of the plurality of lower wiring structures; and an upper wiring layer composed of at least one upper wiring structure in direct contact with the at least one via structure.

公开(公告)号：US20190271918A1

公开(公告)日：2019-09-05

申请号：US15909071

申请日：2018-03-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Sun ,  Guoxiang Ning ,  Meixiong Zhao ,  Erfeng Ding

IPC: G03F7/20 ,  H01L21/308

Abstract: A self-aligned quadruple patterning (SAQP) process for forming semiconductor devices utilizes a look-up table based on lithography and etch profiles to improve the critical dimension(s) of semiconductor structures such as semiconductor fins. The look-up table may include lithography and etch data, including critical dimension (CD) and sidewall angle (SWA) data for intermediate as well as final structures formed during fabrication, and may be used to improve fin CD and fin pitch in device architectures that include densely-arrayed, semi-densely arrayed and nested structures.

公开(公告)号：US10332745B2

公开(公告)日：2019-06-25

申请号：US15597277

申请日：2017-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Sun ,  Ruilong Xie ,  Wenhui Wang ,  Yulu Chen ,  Erik Verduijn ,  Zhengqing John Qi ,  Guoxiang Ning ,  Daniel J. Dechene

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/768 ,  H01L21/3065

Abstract: Methods of forming printed patterns and structures formed using printed patterns. A first line and a second line are lithographically printed in a first layer composed of photoimageable material with a space arranged between the first line and the second line. A dummy assist feature is also lithographically printed in the photoimageable material of the first layer. A second layer underlying the first layer is etched with the first line, the second line, and the dummy assist feature present as an etch mask. The dummy assist feature is arranged on a portion of the space adjacent to the first line and supports the photoimageable material of the first line during etching.

公开(公告)号：US20190056671A1

公开(公告)日：2019-02-21

申请号：US15681007

申请日：2017-08-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Sun ,  John Zhang ,  Shao Beng Law ,  Guoxiang Ning ,  Xunyuan Zhang ,  Ruilong Xie

IPC: G03F7/20 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/544 ,  C23C14/22 ,  C23C16/455

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to overlay mark structures and methods of manufacture. The method includes: forming an overlay mark within a layer of a stack of layers; increasing a density of an upper layer of the stack of layers, above the layer, the increased density protecting the overlay mark; and polishing the upper layer or one or more layers above the upper layer of the stack of layers.

公开(公告)号：US09672312B2

公开(公告)日：2017-06-06

申请号：US14703179

申请日：2015-05-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guido Ueberreiter ,  Paul Ackmann ,  Guoxiang Ning ,  Jui-Hsuan Feng ,  Chin Teong Lim

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081 ,  G06F2217/06 ,  G06F2217/12 ,  G06F2217/14 ,  Y02P90/265

Abstract: A method includes receiving a layout of an integrated circuit that includes a plurality of layers, one of the layers is selected and one or more tile number values are provided. A die area of the integrated circuit is partitioned into a plurality of tiles on the basis of the tile number values. It is determined, on the basis of the layout, if a portion of the selected one of the layers in the tile has an available space for inclusion of a test cell or a dummy cell, and a label indicative of a result is assigned to the tile. It is determined, on the basis of the labels assigned, if one or more space availability criteria are fulfilled and, if fulfilled, the labels are used for placing at least one of one or more test cells and one or more dummy cells in the layout.