公开(公告)号：US20140264613A1

公开(公告)日：2014-09-18

申请号：US13835944

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Xiaodong Yang ,  Jin Ping Liu ,  Yanxiang Liu ,  Xusheng Wu

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a semiconductor substrate includes a shallow trench isolation structure disposed therein. A gate electrode structure overlies semiconductor material of the semiconductor substrate. A first sidewall spacer is formed adjacent to the gate electrode structure, with a first surface of the shallow trench isolation structure exposed and spaced from the first sidewall spacer by a region of the semiconductor material. The first surface of the shallow trench isolation structure is masked with an isolation structure mask. The region of the semiconductor material is free from the isolation structure mask. A recess is etched in the region of the semiconductor material, with the isolation structure mask in place. A semiconductor material is epitaxially grown within the recess to form an epitaxially-grown semiconductor region adjacent to the gate electrode structure.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，半导体衬底包括设置在其中的浅沟槽隔离结构。 栅电极结构覆盖半导体衬底的半导体材料。 形成与栅电极结构相邻的第一侧壁间隔物，其中浅沟槽隔离结构的第一表面暴露并与第一侧壁间隔物隔开半导体材料的区域。 浅沟槽隔离结构的第一表面用隔离结构掩模掩蔽。 半导体材料的区域没有隔离结构掩模。 在半导体材料的区域中蚀刻凹陷，隔离结构掩模就位。 半导体材料在凹槽内外延生长以形成与栅电极结构相邻的外延生长的半导体区域。

公开(公告)号：US10170315B2

公开(公告)日：2019-01-01

申请号：US13943849

申请日：2013-07-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Min-hwa Chi

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/10

Abstract: There is set forth herein a semiconductor device fabricated on a bulk wafer having a local buried oxide region underneath a channel region of a MOSFET. In one embodiment the local buried oxide region can be self-aligned to a gate, and a source/drain region can be formed in a bulk substrate. A local buried oxide region can be formed in a semiconductor device by implantation of oxygen into a bulk region of the semiconductor device followed by annealing.

公开(公告)号：US09666709B2

公开(公告)日：2017-05-30

申请号：US14609105

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiaoli He ,  Yanxiang Liu ,  Jerome Ciavatti ,  Myung Hee Nam

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/739 ,  H01L21/033 ,  H01L21/32

CPC classification number: H01L29/7816 ,  H01L21/0332 ,  H01L21/32 ,  H01L29/0653 ,  H01L29/0882 ,  H01L29/1037 ,  H01L29/41775 ,  H01L29/66356 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7391 ,  H01L29/7835

Abstract: A non-planar semiconductor structure includes a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate, a drain well in each of the raised structures, and a drain in each drain well. The structure further includes an isolation region in each drain well adjacent the drain, each isolation region reaching to a top surface of the corresponding raised structure, and a conductive center gate on each raised structure, the conductive center gate covering a top surface, a front surface and a back surface thereof, and covering a portion of the isolation region opposite the drain. The isolation regions in the drain wells reaching to the raised structure top surface is a result of preserving the isolation region by covering it during fabrication with an HDP oxide to prevent partial removal.

公开(公告)号：US09640538B2

公开(公告)日：2017-05-02

申请号：US14527278

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Min-hwa Chi

IPC: H01L21/3065 ,  H01L27/108 ,  H01L21/308

CPC classification number: H01L27/1087 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/10826 ,  H01L27/10832 ,  H01L27/10867 ,  H01L27/10879

Abstract: Methods for forming an eDRAM with replacement metal gate technology and the resulting device are disclosed. Embodiments include forming first and second dummy electrodes on a substrate, each dummy electrode having spacers at opposite sides and being surrounded by an ILD; removing the first and second dummy electrodes, forming first and second cavities, respectively; forming a hardmask over the substrate, exposing the first cavity; forming a deep trench in the substrate through the first cavity; removing the hardmask; and forming a capacitor in the first cavity and deep trench and concurrently forming an access transistor in the second cavity.

公开(公告)号：US09472554B2

公开(公告)日：2016-10-18

申请号：US13955693

申请日：2013-07-31

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Michael Hargrove ,  Yanxiang Liu ,  Christian Gruensfelder

IPC: H01L21/8234 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823821

Abstract: Integrated circuits that have a FinFET and methods of fabricating the integrated circuits are provided herein. In an embodiment, a method of fabricating an integrated circuit having a FinFET includes providing a substrate comprising fins. The fins include semiconductor material. A first metal oxide layer is formed over sidewall surfaces of the fins. The first metal oxide layer includes a first metal oxide. The first metal oxide layer is recessed to a depth below a top surface of the fins to form a recessed first metal oxide layer. The top surface and sidewall surfaces of the fins at a top portion of the fins are free from the first metal oxide layer. A gate electrode structure is formed over the top surface and sidewall surfaces of the fins at the top portion of the fins. The recessed first metal oxide layer is recessed beneath the gate electrode structure.

Abstract translation: 本文提供了具有FinFET的集成电路和制造集成电路的方法。 在一个实施例中，制造具有FinFET的集成电路的方法包括提供包括鳍片的衬底。 翅片包括半导体材料。 在翅片的侧壁表面上形成第一金属氧化物层。 第一金属氧化物层包括第一金属氧化物。 第一金属氧化物层凹入到翅片的顶表面下方的深度以形成凹陷的第一金属氧化物层。 翅片顶部的翅片的顶表面和侧壁表面不含第一金属氧化物层。 在翅片顶部的翅片的顶表面和侧壁表面上形成栅电极结构。 凹陷的第一金属氧化物层凹陷在栅电极结构下方。

公开(公告)号：US09419126B2

公开(公告)日：2016-08-16

申请号：US13835944

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xiaodong Yang ,  Jin Ping Liu ,  Yanxiang Liu ,  Xusheng Wu

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/78 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a semiconductor substrate includes a shallow trench isolation structure disposed therein. A gate electrode structure overlies semiconductor material of the semiconductor substrate. A first sidewall spacer is formed adjacent to the gate electrode structure, with a first surface of the shallow trench isolation structure exposed and spaced from the first sidewall spacer by a region of the semiconductor material. The first surface of the shallow trench isolation structure is masked with an isolation structure mask. The region of the semiconductor material is free from the isolation structure mask. A recess is etched in the region of the semiconductor material, with the isolation structure mask in place. A semiconductor material is epitaxially grown within the recess to form an epitaxially-grown semiconductor region adjacent to the gate electrode structure.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，半导体衬底包括设置在其中的浅沟槽隔离结构。 栅电极结构覆盖半导体衬底的半导体材料。 形成与栅电极结构相邻的第一侧壁间隔物，其中浅沟槽隔离结构的第一表面暴露并与第一侧壁间隔物隔开半导体材料的区域。 浅沟槽隔离结构的第一表面用隔离结构掩模掩蔽。 半导体材料的区域没有隔离结构掩模。 在半导体材料的区域中蚀刻凹陷，隔离结构掩模就位。 半导体材料在凹槽内外延生长以形成与栅电极结构相邻的外延生长的半导体区域。

公开(公告)号：US09385126B2

公开(公告)日：2016-07-05

申请号：US14742537

申请日：2015-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Min-hwa Chi

IPC: H01L21/00 ,  H01L27/092 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/823892 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/66795

Abstract: Embodiments of the invention provide a semiconductor structure including a finFET having an epitaxial semiconductor region in direct physical contact with a plurality of fins, wherein the epitaxial semiconductor region traverses an insulator layer and is in direct physical contact with the semiconductor substrate. The gate of the finFET is disposed over an insulator layer, such as a buried oxide layer. Methods of forming the semiconductor structure are also included.

公开(公告)号：US20160056265A1

公开(公告)日：2016-02-25

申请号：US14922308

申请日：2015-10-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Yanxiang Liu

IPC: H01L29/66 ,  H01L21/324 ,  H01L21/8234 ,  H01L21/265 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/66575 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/0642 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: An isolation region is formed in a semiconductor substrate to laterally define and electrically isolate a device region and first and second laterally adjacent well regions are formed in the device region. A gate structure is formed above the device region such that the first well region extends below an entirety of the gate structure and a well region interface formed between the first and second well regions is laterally offset from a drain-side edge of the gate structure. Source and drain regions are formed in the device region such that the source region extends laterally from a source-side edge of the gate structure and across a first portion of the first well region to a first inner edge of the isolation region and the drain region extends laterally from the drain-side edge and across a second portion of the first well region.

Abstract translation: 在半导体衬底中形成隔离区域以横向限定并电隔离器件区域，并且在器件区域中形成第一和第二横向相邻阱区域。 在器件区域上方形成栅极结构，使得第一阱区域延伸到整个栅极结构的下方，并且形成在第一阱区域和第二阱区域之间的阱区域界面从栅极结构的漏极侧边缘横向偏移。 源极和漏极区域形成在器件区域中，使得源极区域从栅极结构的源极侧边缘横向延伸并跨越第一阱区域的第一部分延伸到隔离区域的第一内部边缘，并且漏极区域 从排水侧边缘横向延伸并穿过第一井区域的第二部分。

公开(公告)号：US09136330B2

公开(公告)日：2015-09-15

申请号：US13947439

申请日：2013-07-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Johannes M. van Meer ,  Xiaodong Yang ,  Manfred J. Eller

IPC: H01L29/49 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/30625 ,  H01L21/31053 ,  H01L29/0653 ,  H01L29/7846

Abstract: A semiconductor structure with an improved shallow trench isolation (STI) region and method of fabrication is disclosed. The STI region comprises a lower portion filled with oxide and an upper portion comprising a high Young's modulus (HYM) liner disposed on the lower portion and trench sidewalls and filled with oxide. The HYM liner is disposed adjacent to source-drain regions, and serves to reduce stress relaxation within the shallow trench isolation (STI) oxide, which has a relatively low Young's modulus and is soft. Hence, the HYM liner serves to increase the desired stress imparted by the embedded stressor source-drain regions, which enhances carrier mobility, thus increasing semiconductor performance.

Abstract translation: 公开了具有改进的浅沟槽隔离（STI）区域和制造方法的半导体结构。 STI区域包括填充有氧化物的下部分和包括设置在下部分上的高杨氏模量（HYM）衬垫和沟槽侧壁并填充有氧化物的上部部分。 HYM衬垫设置在源 - 漏区附近，用于减少浅沟槽隔离（STI）氧化物中的应力松弛，其具有较低的杨氏模量并且柔软。 因此，HYM衬垫用于增加由嵌入式应力源源极 - 漏极区域施加的所需应力，这增强了载流子迁移率，从而提高了半导体性能。

公开(公告)号：US20150221770A1

公开(公告)日：2015-08-06

申请号：US14686228

申请日：2015-04-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes M. van Meer ,  Michael J. Hargrove ,  Christian Gruensfelder ,  Yanxiang Liu ,  Srikanth B. Samavedam

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7856 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1608 ,  H01L29/66795 ,  H01L29/7855

Abstract: Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of silicon fins for a FinFET device, the FinFET device comprising: a set of gate structures formed over a substrate, each of the set of gate structures including a capping layer and a set of spacers; an oxide fill formed over the set of gate structures; a set of openings formed in the device by removing the capping layer and the set of spacers from one or more of the set of gate structures; a silicon material epitaxially grown within the set of openings in the device and then planarized; and wherein the oxide fill is etched to expose the silicon material and form the set of fins.

Abstract translation: 提供了用于在器件（例如，鳍式场效应晶体管器件（FinFET））中实现硅鳍外延生长的方法。 具体地，提供了用于形成用于FinFET器件的一组硅散热片的方法，所述FinFET器件包括：在衬底上形成的一组栅极结构，所述一组栅极结构中的每一个包括覆盖层和一组间隔物; 在该组栅极结构上形成的氧化物填充物; 通过从所述一组或多组所述栅极结构中去除所述覆盖层和所述一组间隔物而在所述器件中形成的一组开口; 外延生长在器件中的开口组内然后平坦化的硅材料; 并且其中蚀刻氧化物填充物以暴露硅材料并形成该组散热片。