公开(公告)号：US20150123212A1

公开(公告)日：2015-05-07

申请号：US14070624

申请日：2013-11-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiang Hu ,  Lokesh Subramany ,  Alok Vaid ,  Sipeng Gu ,  Akshey Sehgal

IPC: H01L21/308 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L23/544 ,  H01L21/3083 ,  H01L21/3086 ,  H01L22/30 ,  H01L27/0886 ,  H01L29/0692 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for providing a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. A previously deposited amorphous carbon layer can be removed from over a mandrel that has been previously formed on a subset of a substrate, such as using a photoresist. A pad hardmask can be formed over the mandrel on the subset of the substrate. This formation results in the subset of the substrate having the pad hardmask covering the mandrel thereon and the remainder of the substrate having the amorphous carbon layer covering the mandrel thereon. This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers.

Abstract translation: 公开了一种用于提供与翅片场效应晶体管（FinFET）器件的一组翅片相邻的平面计量垫的方法。 先前沉积的非晶碳层可以从预先形成在基底的子集上的心轴上去除，例如使用光致抗蚀剂。 衬垫硬掩模可以在衬底的子集上的心轴上形成。 这种形成导致衬底的子集具有覆盖其上的心轴的衬垫硬掩模，并且具有覆盖其上的心轴的无定形碳层的衬底的其余部分。 该无定形碳层可以在基体的其余部分上从心轴上除去，允许在其中形成一组翅片，而无定形碳层保持该组翅片不会形成在其所覆盖的基底部分中。

公开(公告)号：US20150115267A1

公开(公告)日：2015-04-30

申请号：US14067204

申请日：2013-10-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sipeng Gu ,  Xiang Hu ,  Alok Vaid ,  Lokesh Subramany ,  Akshey Sehgal

IPC: G01R31/26 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L22/30 ,  G01R31/2621 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924

Abstract: Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.

公开(公告)号：US10121711B2

公开(公告)日：2018-11-06

申请号：US14816708

申请日：2015-08-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sipeng Gu ,  Xiang Hu ,  Alok Vaid ,  Lokesh Subramany ,  Akshey Sehgal

IPC: H01L29/10 ,  H01L29/76 ,  H01L21/82 ,  H01L21/66 ,  G01R31/26 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092

Abstract: Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.

公开(公告)号：US20160358851A1

公开(公告)日：2016-12-08

申请号：US14729188

申请日：2015-06-03

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Sunil Kumar Singh ,  Ravi Prakash Srivastava ,  Xusheng Wu ,  Akshey Sehgal ,  Teck Jung Tang

IPC: H01L23/522 ,  H01L21/02 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/02282 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76811 ,  H01L23/53238 ,  H01L23/53295

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes depositing an organic dielectric material overlying a semiconductor substrate for forming an organic interlayer dielectric (OILD) layer. An opening is formed in the OILD layer and a conductive metal fill is deposited in the opening for forming a metal line and/or a via.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，制造集成电路的方法包括沉积覆盖在用于形成有机层间电介质（OILD）层的半导体衬底上的有机电介质材料。 在OILD层中形成开口，并且在用于形成金属线和/或通孔的开口中沉积导电金属填充物。

公开(公告)号：US09293363B2

公开(公告)日：2016-03-22

申请号：US14805443

申请日：2015-07-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil K. Singh ,  Ravi P. Srivastava ,  Mark A. Zaleski ,  Akshey Sehgal

IPC: H01L29/66 ,  H01L21/4763 ,  H01L21/311 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/3213

CPC classification number: H01L23/528 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/31051 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76892 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.

公开(公告)号：US20150340296A1

公开(公告)日：2015-11-26

申请号：US14816708

申请日：2015-08-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sipeng Gu ,  Xiang Hu ,  Alok Vaid ,  Lokesh Subramany ,  Akshey Sehgal

IPC: H01L21/66 ,  H01L27/088

CPC classification number: H01L22/30 ,  G01R31/2621 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924

Abstract: Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.

Abstract translation: 公开了一种用于提供具有与翅片场效应晶体管（FinFET）器件的一组翅片相邻的平面度量垫的衬底的方法。 具体地说，FinFET器件包括鳍式衬底和在FinFET器件的度量测量区域中与衬底相邻的衬底上形成的平面度量垫。 处理步骤包括在衬底上形成第一硬掩模，在FinFET器件的测量测量区域中的第一硬掩模的一部分上形成光致抗蚀剂，在形成光致抗蚀剂之后，在与测量测量区域相邻的区域中残留的部分去除第一硬掩模 在衬底中图案化一组开口以在邻近测量测量区域的区域中的FinFET器件中形成一组鳍片，在FinFET器件上沉积氧化物层，以及平坦化FinFET器件，以形成平面度量板 计量测量领域。

公开(公告)号：US20150332959A1

公开(公告)日：2015-11-19

申请号：US14805443

申请日：2015-07-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil K. Singh ,  Ravi P. Srivastava ,  Mark A. Zaleski ,  Akshey Sehgal

IPC: H01L21/768

CPC classification number: H01L23/528 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/31051 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76892 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.

Abstract translation: 本发明的实施例提供了一种用于BEOL（后端）集成的半导体结构。 定向自组装（DSA）材料被沉积并退火以形成两个不同的相位区域。 选择性地去除一个相区，并且剩余的相区用作在金属和/或电介质的下层中形成空腔的掩模。 然后重复该过程以形成具有由电介质区域分离的金属图案的复杂结构。

公开(公告)号：US09117822B1

公开(公告)日：2015-08-25

申请号：US14264163

申请日：2014-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil K. Singh ,  Ravi P. Srivastava ,  Mark A. Zaleski ,  Akshey Sehgal

IPC: H01L29/66 ,  H01L21/4763 ,  H01L21/31 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/3213

CPC classification number: H01L23/528 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/31051 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76892 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.

Abstract translation: 本发明的实施例提供了一种用于BEOL（后端）集成的半导体结构。 定向自组装（DSA）材料被沉积并退火以形成两个不同的相位区域。 选择性地去除一个相区，并且剩余的相区用作在金属和/或电介质的下层中形成空腔的掩模。 然后重复该过程以形成具有由电介质区域分离的金属图案的复杂结构。

公开(公告)号：US10818557B2

公开(公告)日：2020-10-27

申请号：US16026130

申请日：2018-07-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sipeng Gu ,  Akshey Sehgal ,  Xinyuan Dou ,  Sunil K. Singh ,  Ravi P. Srivastava ,  Haiting Wang ,  Scott H. Beasor

IPC: H01L21/8234 ,  H01L29/423 ,  H01L23/48 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/49 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/66 ,  H01L29/08

Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor structure including two source/drain regions; a metal gate positioned on the semiconductor structure adjacent to and between the source/drain regions; a metal cap with a different metal composition than the metal gate and having a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm positioned on the metal gate; a first dielectric cap layer positioned above the semiconductor structure; an inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein an upper surface of the ILD has a greater height above the semiconductor structure than an upper surface of the metal gate; a second dielectric cap layer positioned on the ILD and above the metal cap; and a contact on and in electrical contact with the metal cap.

公开(公告)号：US10347528B1

公开(公告)日：2019-07-09

申请号：US15912975

申请日：2018-03-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sunil K. Singh ,  Ravi P. Srivastava ,  Sipeng Gu ,  Akshey Sehgal

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Methods of forming an interconnect of an IC are disclosed. The methods etch a wire trench opening partially into an ILD layer using a hard mask, and form a metal liner sidewall spacer on sidewalls of the wire trench opening, prior to etching via openings that create a via-wire opening with the wire trench opening. The metal liner sidewall spacer protects against chamfering during the via etch and/or removal of an etch stop layer over conductive structures in an underlying ILD layer. In one embodiment, a barrier liner is deposited over the metal liner sidewall spacer, creating a double layered sidewall spacer on the sidewalls of the wire trench opening portion of the via-wire opening. A conductor is deposited to form a unitary via-wire conductive structure. An interconnect includes the double layered sidewall spacer on the sidewalls of a wire trench opening portion of the via-wire conductive structure.