公开(公告)号：US09437496B1

公开(公告)日：2016-09-06

申请号：US14727219

申请日：2015-06-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Brian J. Greene ,  Edward P. Maciejewski ,  Kevin McStay ,  Shreesh Narasimha ,  Chengwen Pei ,  Werner A. Rausch

IPC: H01L29/10 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L29/66545

Abstract: A semiconductor device such as a FinFET includes a plurality of fins formed upon a substrate and a gate covering a portion of the fins. Diamond-shaped volumes are formed on the sidewalls of the fins by epitaxial growth which may be limited to avoid merging of the volumes or where the epitaxy volumes have merged. Because of the difficulties in managing merging of the diamond-shaped volumes, a controlled merger of the diamond-shaped volumes includes depositing an amorphous semiconductor material upon the diamond-shaped volumes and a crystallization process to crystallize the deposited semiconductor material on the diamond-shaped volumes to fabricate controllable and uniformly merged source drain.

Abstract translation: 诸如FinFET的半导体器件包括形成在衬底上的多个鳍片和覆盖鳍片的一部分的栅极。 通过外延生长在翅片的侧壁上形成菱形体积，其可以被限制以避免体积的合并或外延体积合并的位置。 由于难以管理菱形体积的合并，钻石形容积的受控合并包括在金刚石体积上沉积非晶半导体材料和结晶过程以将沉积的半导体材料结晶在菱形体上 体积来制造可控和均匀合并的源极漏极。

公开(公告)号：US20160172314A1

公开(公告)日：2016-06-16

申请号：US14566773

申请日：2014-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Geng Wang

IPC: H01L23/00 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L23/564 ,  H01L21/26586 ,  H01L21/743 ,  H01L21/76229 ,  H01L21/84 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/66181 ,  H01L29/945 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure is provided that includes a semiconductor on insulator (SOI) substrate comprising a bottom semiconductor layer, an epitaxial semiconductor layer present on the bottom semiconductor layer, a buried insulator layer present on the epitaxial semiconductor layer, and a top semiconductor layer present on the buried insulator layer. A deep trench moat (DTMOAT) is disposed in the SOI substrate and has a bottom surface contacting a dopant region of the bottom semiconductor layer. A moat contact electrically connecting the DTMOAT to the epitaxial semiconductor layer of the SOI substrate. Charges accumulated in the DTMOAT can be discharged through the heavily doped epitaxial semiconductor layer to ground, thus preventing the DTMOAT failure caused by the process-induced charge accumulation.

Abstract translation: 提供一种半导体结构，其包括半导体绝缘体（SOI）衬底，其包括底部半导体层，存在于底部半导体层上的外延半导体层，存在于外延半导体层上的掩埋绝缘体层以及存在于外部半导体层上的顶部半导体层 埋层绝缘体层。 深沟槽沟（DTMOAT）设置在SOI衬底中并具有与底部半导体层的掺杂区接触的底面。 将DTMOAT电连接到SOI衬底的外延半导体层的护套接点。 在DTMOAT中累积的电荷可以通过重掺杂的外延半导体层放电到地面，从而防止由过程引起的电荷积累引起的DTMOAT故障。

公开(公告)号：US09343320B2

公开(公告)日：2016-05-17

申请号：US14098650

申请日：2013-12-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Geng Wang

IPC: H01L27/108 ,  H01L21/306 ,  H01L21/308 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/84 ,  H01L29/66 ,  H01L29/94 ,  H01L27/12

CPC classification number: H01L21/30604 ,  H01L21/3081 ,  H01L21/84 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

Abstract: Dummy deep trenches can be formed within a logic device region in which logic devices are to be formed while deep trench capacitors are formed within a memory device region. Semiconductor fins are formed over a top surface prior to forming trenches, and disposable material is filled around said semiconductor fins. A top surface of said disposable filler material layer can be coplanar with a top surface of said semiconductor fins, which eases deep trench formation. Conductive material portions of the dummy deep trenches can be recessed to avoid electrical contact with semiconductor fins within the logic device region, while an inner electrode of each deep trench can contact a semiconductor fin within the memory device region. A dielectric material portion can be formed above each conductive material portion of a dummy deep trench.

Abstract translation: 虚拟深沟槽可以形成在其中将在存储器件区域内形成深沟槽电容器的逻辑器件区域内形成逻辑器件。 半导体翅片在形成沟槽之前形成在顶表面上，并且一次性材料填充在所述半导体鳍片周围。 所述一次性填充材料层的顶表面可以与所述半导体鳍片的顶表面共面，这使得深沟槽形成更容易。 虚拟深沟槽的导电材料部分可以凹入以避免与逻辑器件区域内的半导体鳍片的电接触，而每个深沟槽的内部电极可接触存储器件区域内的半导体鳍片。 可以在虚拟深沟槽的每个导电材料部分上方形成电介质材料部分。

公开(公告)号：US09228994B1

公开(公告)日：2016-01-05

申请号：US14452741

申请日：2014-08-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Geng Wang

IPC: H01L29/40 ,  G01N33/487 ,  H01L27/088 ,  H01L29/66 ,  H01L29/41

CPC classification number: G01N27/4145 ,  G01N33/48721 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/413

Abstract: A nanoscale electrode device can be fabricated by forming a pair of semiconductor fins laterally spaced from each other by a uniform distance and formed on a substrate. The pair of semiconductor fins can function as a pair of electrodes that can be biased to detect the leakage current through a nanoscale string to pass therebetween. A nanochannel having a uniform separation distance is formed between the pair of semiconductor fins. The nanochannel may be defined by a gap between a pair of raised active regions formed on the pair of semiconductor fins, or between proximal sidewalls of the pair of semiconductor fins. An opening is formed through the portion of the substrate underlying the region of the nanochannel to enable passing of a nanoscale string.

Abstract translation: 可以通过在基板上形成相互间隔一定距离的一对半导体翅片来制造纳米尺寸的电极装置。 该对半导体散热片可以用作一对电极，该电极可被偏置以检测通过纳米尺度串的通过的漏电流。 在一对半导体鳍片之间形成具有均匀间隔距离的纳米通道。 纳米通道可以由形成在一对半导体鳍片上的一对凸起的有源区域之间或在该对半导体鳍片的近侧壁之间的间隙限定。 通过在纳米通道的区域下方的衬底的部分形成开口，以使得能够通过纳米级的串。

公开(公告)号：US10199463B2

公开(公告)日：2019-02-05

申请号：US15906355

申请日：2018-02-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Waikin Li ,  Chengwen Pei ,  Ping-Chuan Wang

IPC: H01L29/06 ,  H01L29/423 ,  H01L27/108 ,  H01L23/522 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/66 ,  H01L29/775 ,  H01L49/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator. At least one bitline extending on a top of the plurality of vertical nanowires and in electrical contact therewith; and at least one wordline formed on vertical sidewalls of the plurality of vertical nanowires and separated therefrom by the dielectric material.

公开(公告)号：US20180366562A1

公开(公告)日：2018-12-20

申请号：US15627715

申请日：2017-06-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng Wu ,  Chengwen Pei ,  Ziyan Xu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: The disclosure is directed to methods of forming an integrated circuit structure and a related structure. One method may include: forming a gate structure over a fin, the fin being formed over a substrate and the gate structure defining a channel region beneath the gate structure within the fin; forming a notch within the fin and beneath the channel region by laterally etching the fin on opposing sides of the channel region; forming a rare-earth oxide (REO) within the notch and extending along a top surface of the fin outside of the notch; and forming a source region and a drain region on opposing sides of the channel region and over the REO that is disposed along the top surface of the fin.

公开(公告)号：US20180122795A1

公开(公告)日：2018-05-03

申请号：US15338512

申请日：2016-10-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ziyan Xu ,  Chengwen Pei ,  Xusheng Wu

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/51 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L21/823418 ,  H01L27/10829 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/517 ,  H01L29/66553 ,  H01L29/7835

Abstract: An asymmetric transistor may be used for controlling a memory cell. The asymmetric transistor may include at least one gate stack having bottom to top: a gate dielectric layer having a planar upper surface and a uniform thickness extending atop the entirety of the device channel, a dielectric threshold voltage adjusting element including: a sloped dielectric element located on the planar upper surface of the gate dielectric layer, and a sidewall dielectric layer extending from the sloped dielectric element along a first sidewall of the opening space, and a gate conductor located atop an upper surface of the sloped dielectric element and along a side of the sidewall dielectric layer. The dielectric threshold voltage adjusting element creates a threshold voltage that is lower in a writing mode than in a storage mode of the memory cell.

公开(公告)号：US09755013B2

公开(公告)日：2017-09-05

申请号：US14692881

申请日：2015-04-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wai-Kin Li ,  Chengwen Pei ,  Ping-Chuan Wang

IPC: H01L49/02 ,  H01L27/06 ,  H01L21/8238

CPC classification number: H01L28/92 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0629

Abstract: High density capacitor structures based on an array of semiconductor nanorods are provided. The high density capacitor structure can be a plurality of capacitors in which each of the semiconductor nanorods serves as a bottom electrode for one of the plurality of capacitors, or a large-area metal-insulator-metal (MIM) capacitor in which the semiconductor nanorods serve as a support structure for a bottom electrode of the MIM capacitor subsequently formed.

公开(公告)号：US09490223B2

公开(公告)日：2016-11-08

申请号：US14566773

申请日：2014-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Geng Wang

IPC: H01L21/70 ,  H01L23/00 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L23/564 ,  H01L21/26586 ,  H01L21/743 ,  H01L21/76229 ,  H01L21/84 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/66181 ,  H01L29/945 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure is provided that includes a semiconductor on insulator (SOI) substrate comprising a bottom semiconductor layer, an epitaxial semiconductor layer present on the bottom semiconductor layer, a buried insulator layer present on the epitaxial semiconductor layer, and a top semiconductor layer present on the buried insulator layer. A deep trench moat (DTMOAT) is disposed in the SOI substrate and has a bottom surface contacting a dopant region of the bottom semiconductor layer. A moat contact electrically connecting the DTMOAT to the epitaxial semiconductor layer of the SOI substrate. Charges accumulated in the DTMOAT can be discharged through the heavily doped epitaxial semiconductor layer to ground, thus preventing the DTMOAT failure caused by the process-induced charge accumulation.

Abstract translation: 提供一种半导体结构，其包括半导体绝缘体（SOI）衬底，其包括底部半导体层，存在于底部半导体层上的外延半导体层，存在于外延半导体层上的掩埋绝缘体层以及存在于外部半导体层上的顶部半导体层 埋层绝缘体层。 深沟槽沟（DTMOAT）设置在SOI衬底中并具有与底部半导体层的掺杂区接触的底面。 将DTMOAT电连接到SOI衬底的外延半导体层的护套接点。 在DTMOAT中累积的电荷可以通过重掺杂的外延半导体层放电到地面，从而防止由过程引起的电荷积累引起的DTMOAT故障。

公开(公告)号：US09337289B2

公开(公告)日：2016-05-10

申请号：US14571628

申请日：2014-12-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhengwen Li ,  Dechao Guo ,  Randolph F. Knarr ,  Chengwen Pei ,  Gan Wang ,  Yanfeng Wang ,  Keith Kwong Hon Wong ,  Jian Yu ,  Jun Yuan

IPC: H01L21/70 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42368 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/78 ,  H01L29/7833

Abstract: In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor.