公开(公告)号：US20170200792A1

公开(公告)日：2017-07-13

申请号：US14993537

申请日：2016-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chang Ho MAENG ,  Andy WEI ,  Anthony OZZELLO ,  Bharat KRISHNAN ,  Guillaume BOUCHE ,  Haifeng SHENG ,  Haigou HUANG ,  Huang LIU ,  Huy M. CAO ,  Ja-Hyung HAN ,  SangWoo LIM ,  Kenneth A. BATES ,  Shyam PAL ,  Xintuo DAI ,  Jinping LIU

IPC: H01L29/40 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/401 ,  H01L21/02126 ,  H01L21/02282 ,  H01L21/28229 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/78

Abstract: Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiO2 layer; forming a metal layer over the SiO2 layer; and planarizing the metal and SiO2 layers down to the gate cap layer.

公开(公告)号：US20170047282A1

公开(公告)日：2017-02-16

申请号：US14822597

申请日：2015-08-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhiguo SUN ,  Qiang FANG ,  Huang LIU ,  Haigou HUANG ,  Jiehui SHU ,  Jin Ping LIU

IPC: H01L23/528 ,  H01L21/321 ,  H01L23/532 ,  H01L23/522 ,  H01L21/3065 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/3065 ,  H01L21/321 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76853 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53204 ,  H01L23/53238 ,  H01L23/53266

Abstract: Reducing liner corrosion during metallization of semiconductor devices at BEOL includes providing a starting metallization structure, the structure including a bottom layer of dielectric material with a via therein, a liner lining the via and extending over upper edges thereof, the lined via over filled with a conductive material, recessing the conductive material down to the liner, further selectively recessing the conductive material below the upper edges of the via without damaging the liner, and forming a cap of the liner material on the conductive material.

Abstract translation: 在BEOL的半导体器件的金属化期间减少衬里腐蚀包括提供起始金属化结构，该结构包括介电材料的底层，其中具有通孔，衬套衬套通孔并在其上边缘延伸的衬里，衬里通孔填充有 导电材料将导电材料向下凹入衬垫，进一步选择性地使导电材料在通孔的上边缘下方凹陷，而不损坏衬垫，并且在导电材料上形成衬垫材料的帽。

公开(公告)号：US20150364336A1

公开(公告)日：2015-12-17

申请号：US14306920

申请日：2014-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong YU ,  Haigou HUANG ,  Jin Ping LIU ,  Huang LIU

IPC: H01L21/3105 ,  H01L21/311

CPC classification number: H01L21/31055 ,  H01L21/02318 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/823821 ,  H01L21/823842

Abstract: A semiconductor structure with mixed n-type and p-type non-planar transistors includes a residual overlapping mask bump on one or more of the dummy gates. A dielectric layer is created over the structure having a top surface above the residual bump, for example, using a blanket deposition and chemical-mechanical underpolish (i.e., stopping before exposing the gate cap). The residual bump is then transformed into a same material as the dielectric, either in its entirety and then removing the combined dielectric, or by removing the dielectric first and partly removing the residual bump, the remainder of which is then transformed and the dielectric removed. In either case, the structure is planarized for further processing.

Abstract translation: 具有混合n型和p型非平面晶体管的半导体结构包括在一个或多个虚拟栅极上的残留重叠掩模凸块。 例如，使用覆盖沉积和化学机械的低估（即，在暴露栅极盖之前停止），在该结构上方形成介电层，该顶表面具有顶部表面。 然后将剩余的凸块转变成与电介质完全相同的材料，然后去除组合的电介质，或者通过首先去除电介质并部分去除残余凸块，然后将其余部分转化并除去电介质。 在任一种情况下，将结构平坦化用于进一步处理。

公开(公告)号：US20150093877A1

公开(公告)日：2015-04-02

申请号：US14042997

申请日：2013-10-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haigou HUANG ,  Huang LIU ,  Hongliang SHEN ,  Yongsik MOON

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/31053 ,  H01L21/31055

Abstract: A method for fabricating a semiconductor device is provided, including forming a mask on a surface of a semiconductor substrate, creating isolation trenches within the substrate, and removing the mask from the substrate before depositing an insulating material within the trenches. The insulating material is then planarized to form a surface that is substantially coplanar with the surface of the semiconductor substrate.

Abstract translation: 提供了一种制造半导体器件的方法，包括在半导体衬底的表面上形成掩模，在衬底内形成隔离沟槽，以及在沟槽内淀积绝缘材料之前从衬底去除掩模。 然后将绝缘材料平坦化以形成与半导体衬底的表面基本上共面的表面。