公开(公告)号：US20160141379A1

公开(公告)日：2016-05-19

申请号：US14541754

申请日：2014-11-14

Applicant: GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hui ZANG ,  Balasubramanian PRANATHARTHIHARAN

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/3213 ,  H01L29/40 ,  H01L21/311

CPC classification number: H01L29/41783 ,  H01L21/28008 ,  H01L21/76801 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/401 ,  H01L29/785

Abstract: Devices and methods for forming semiconductor devices with middle of line capacitance reduction in self-aligned contact process flow and fabrication are provided. One method includes, for instance: obtaining a wafer with at least one source, drain, and gate; forming a first contact region over the at least one source and a second contact region over the at least one drain; and forming at least one first and second small contact over the first and second contact regions. One intermediate semiconductor device includes, for instance: a wafer with a gate, source region, and drain region; at least one first contact region positioned over a portion of the source; at least one second contact region positioned over a portion of the drain; at least one first small contact positioned above the first contact region; and at least one second small contact positioned above the second contact region.

Abstract translation: 提供了用于形成具有自对准接触工艺流程和制造中线路电容减小的半导体器件的器件和方法。 一种方法包括例如：获得具有至少一个源极，漏极和栅极的晶片; 在所述至少一个源极上形成第一接触区域，以及在所述至少一个漏极上形成第二接触区域; 以及在所述第一和第二接触区域上形成至少一个第一和第二小接触。 一个中间半导体器件包括例如：具有栅极，源极区和漏极区的晶片; 位于所述源的一部分上方的至少一个第一接触区域; 至少一个第二接触区域位于所述排水管的一部分上方; 位于所述第一接触区域上方的至少一个第一小接触件; 以及位于第二接触区域上方的至少一个第二小接触件。

公开(公告)号：US20160111514A1

公开(公告)日：2016-04-21

申请号：US14515141

申请日：2014-10-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/4958 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A non-planar semiconductor structure includes an ultra-low resistance gate structure. The non-planar structure includes a semiconductor substrate and raised semiconductor structures coupled to the substrate, a lower portion of the raised structures surrounded by a layer of isolation material. The structure further includes gate structures surrounding an upper portion of the raised structures, the gate structures including a conductive material and a layer of work function material present only in a limited area surrounding each raised structure. The limited area of work function material is achieved in fabrication by including dummy gate structures covering a layer of selectively removable material above the raised structures and a layer of hard mask material above the selectively removable layer, removing the selectively removable layer with the dummy gate structures, filling the resulting gate openings with work function material and then removing most of it, using the layer of hard mask material to delimit the limited area of work function material.

Abstract translation: 非平面半导体结构包括超低电阻门结构。 非平面结构包括半导体衬底和耦合到衬底的凸起的半导体结构，由隔离材料层包围的凸起结构的下部。 该结构还包括围绕凸起结构的上部的栅极结构，栅极结构包括仅在围绕每个凸起结构的有限区域中的导电材料和功函数层。 功能材料的有限面积通过包括覆盖凸起结构之上的可选择性地移除的材料层的虚拟栅极结构和在可选择性移除的层之上的硬掩模材料层来实现，用虚拟栅极结构去除可选择性移除的层 ，用功能材料填充所得到的门开口，然后使用硬掩模材料层去除大部分门开口以界定功能材料的有限区域。

公开(公告)号：US20160111339A1

公开(公告)日：2016-04-21

申请号：US14516674

申请日：2014-10-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG

IPC: H01L21/8238 ,  H01L21/321 ,  H01L29/08 ,  H01L21/285 ,  H01L29/45 ,  H01L27/092

CPC classification number: H01L21/823814 ,  H01L21/28518 ,  H01L21/28531 ,  H01L21/28568 ,  H01L21/321 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/45

Abstract: Contact liners for integrated circuits and fabrication methods thereof are presented. The methods include: fabricating an integrated circuit structure having a first transistor having at least one of a p-type source region or a p-type drain region and a second transistor having at least one of an n-type source region or an n-type drain region, and the fabricating including: forming a contact liner at least partially over both the first transistor and the second transistor, the contact liner including a first contact liner material and a second contact liner material, wherein the first contact liner material is selected to facilitate electrical connection to the at least one p-type source region or p-type drain region of the first transistor, and the second contact liner material is selected to facilitate electrical connection to the at least one n-type source region or n-type drain region of the second transistor.

Abstract translation: 介绍了集成电路的接触衬垫及其制造方法。 所述方法包括：制造具有第一晶体管的集成电路结构，所述第一晶体管具有p型源极区或p型漏极区中的至少一个，以及具有n型源区或n型源区中至少一个的第二晶体管， 并且所述制造包括：至少部分地在所述第一晶体管和所述第二晶体管两者上形成接触衬垫，所述接触衬垫包括第一接触衬垫材料和第二接触衬里材料，其中所述第一接触衬里材料被选择 以促进与第一晶体管的至少一个p型源区或p型漏极区的电连接，并且选择第二接触衬垫材料以促进与至少一个n型源区或n型源区的电连接。 型漏极区域。

公开(公告)号：US20200152749A1

公开(公告)日：2020-05-14

申请号：US16742981

申请日：2020-01-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Guowei XU ,  Keith TABAKMAN ,  Viraj SARDESAI

IPC: H01L29/417 ,  H01L27/088 ,  H01L21/768 ,  H01L21/311 ,  H01L21/28 ,  H01L29/66

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and/or drain metallization features; spacers on sidewalls of the gate structures and composed of a first material and a second material; and contacts in electrical contact with the source and/or drain metallization features, and separated from the gate structures by the spacers.

公开(公告)号：US20200083363A1

公开(公告)日：2020-03-12

申请号：US16126775

申请日：2018-09-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Laertis ECONOMIKOS ,  Jiehui SHU ,  Ruilong XIE

IPC: H01L29/78 ,  H01L29/66 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06

Abstract: A device including oxide spacer in a contact over active gates (COAG) and method of production thereof. Embodiments include first gate structures over a fin of a substrate and second gate structures, each over an outer portion of the fin and a shallow trench isolation (STI) layer adjacent to the fin; a first raised source/drain (RSD) in a portion of the fin between the first gate structures and a second RSD in the portion of the fin between the first and second gate structures; a metal liner over the first and second RSD and on sidewall portions of the first and second gate structures; a metal layer over the metal liner; and an interlayer dielectric (ILD) over the metal liner and portions of the first and second gate structures.

公开(公告)号：US20190081155A1

公开(公告)日：2019-03-14

申请号：US15703221

申请日：2017-09-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Kangguo CHENG ,  Nicolas LOUBET ,  Xin MIAO ,  Pietro MONTANINI ,  John ZHANG ,  Haigou HUANG ,  Jianwei PENG ,  Sipeng GU ,  Hui ZANG ,  Yi QI ,  Xusheng WU

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A method of forming nanosheet and nanowire transistors includes the formation of alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si), where the germanium content within respective layers of the silicon germanium is systemically varied in order to mediate the selective etching of these layers. The germanium content is controlled such that recessed regions created by partial removal of the silicon germanium layers have uniform lateral dimensions, and the backfilling of such recessed regions with an etch selective material results in the formation of a robust etch barrier.

公开(公告)号：US20190081049A1

公开(公告)日：2019-03-14

申请号：US15702243

申请日：2017-09-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L23/535 ,  H01L21/8238 ,  H01L21/285

Abstract: A method of forming a VNW SRAM device with a vertical cross-couple/PD/PU contact landed on a PD/PU gate and a bottom nRX and pRX interface and the resulting device are provided. Embodiments include forming a first and a second bottom nRX and pRX over an NW upon a p-sub, the pRX formed between the nRX; forming fins over the first nRX, the first pRX, the second pRX, and over the second nRX; forming a first GAA perpendicular to and over the second pRX and nRX, a second GAA perpendicular to and over the first nRX and pRX, a third GAA perpendicular to and over a portion the first nRX, and a fourth GAA perpendicular to and over a portion of the second nRX; and forming a first and a second metal gate contact on the first GAA, nRX, and pRX and on the second GAA, pRX, and nRX, respectively.

公开(公告)号：US20190027575A1

公开(公告)日：2019-01-24

申请号：US15656542

申请日：2017-07-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Haigou Huang

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L21/762

CPC classification number: H01L29/518 ,  H01L21/76224 ,  H01L29/495 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66613 ,  H01L29/78 ,  H01L29/7831

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor device with reduced gate height budget and methods of manufacture. The method includes: forming a plurality of gate structures on a substrate; recessing material of the plurality of gate structures to below a surface of an insulator material; forming trenches in the insulator material and underlying material adjacent to sidewalls of the plurality of gate structures; and filling the recesses and trenches with a capping material.

公开(公告)号：US20180286873A1

公开(公告)日：2018-10-04

申请号：US15995896

申请日：2018-06-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Min-hwa CHI

IPC: H01L27/11 ,  H01L21/311 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L27/1104 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/535 ,  H01L27/11 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices for forming conductive paths between fins for contact-to-gate shorting. One method includes, for instance: obtaining wafer with a substrate, at least one fin, at least one hard mask, and an oxide layer; etching the oxide layer to reveal at least one of a portion of the hard masks; forming sacrificial pillars over the substrate; forming sacrificial gates, wherein at least one sacrificial gate contacts at least one sacrificial pillar; growing an epitaxial layer between the at least one sacrificial gate and the at least one sacrificial pillar; starting a RMG process on the sacrificial gates; etching to remove the sacrificial pillars and form pillar openings; and completing the RMG process to fill the pillar openings and the gate openings with a metal.

公开(公告)号：US20180277655A1

公开(公告)日：2018-09-27

申请号：US15994614

申请日：2018-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Srikanth Balaji SAMAVEDAN ,  Manfred ELLER ,  Min-hwa CHI ,  Hui ZANG

IPC: H01L29/66 ,  H01L21/308 ,  H01L21/306 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/30604 ,  H01L21/3085 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of reducing parasitic capacitance includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with fin(s) thereon, the fin(s) having at least two dummy transistors integrated therewith and separated by a dielectric region, the dummy transistors including dummy gates with spacers and gate caps, the fin(s) having ends tucked by the dummy gates. The method further includes removing the dummy gates and gate caps, resulting in gate trenches, protecting area(s) of the structure during fabrication process(es) where source/drain parasitic capacitance may occur, and forming air-gaps at a bottom portion of unprotected gate trenches to reduce parasitic capacitance. The resulting semiconductor structure includes a semiconductor substrate with fin(s) thereon, FinFET(s) integral with the fin(s), the FinFET(s) including a gate electrode, a gate liner lining the gate electrode, and air-gap(s) in gate trench(es) of the FinFET(s), reducing parasitic capacitance by at least about 75 percent as compared to no air-gaps.