公开(公告)号：US20180138123A1

公开(公告)日：2018-05-17

申请号：US15351750

申请日：2016-11-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jim Shih-Chun Liang ,  Keith Kwong Hon Wong

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/28556 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76865 ,  H01L21/76879 ,  H01L21/76889 ,  H01L23/485 ,  H01L23/53209 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: Aspects of the present disclosure include a semiconductor device which includes a dielectric layer deposited over a conductive region and an interconnect electrically connecting the conductive region with a top surface of the dielectric layer. The interconnect includes a barrier layer extending from an interior of the dielectric layer to the conductive region and covering the conductive region. The barrier layer encases a cobalt plug. The interconnect includes a tungsten cap on an upper surface of the cobalt plug. The tungsten cap is coplanar with an upper surface of the dielectric layer. A method of manufacturing the semiconductor device is also provided.

公开(公告)号：US09472640B2

公开(公告)日：2016-10-18

申请号：US14698206

申请日：2015-04-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dechao Guo ,  Shu-Jen Han ,  Yu Lu ,  Keith Kwong Hon Wong

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/778 ,  H01L29/16 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/04 ,  H01L21/306 ,  H01L51/00 ,  H01L51/05

CPC classification number: H01L29/66045 ,  H01L21/02527 ,  H01L21/043 ,  H01L21/044 ,  H01L21/30604 ,  H01L29/1606 ,  H01L29/41733 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/78684 ,  H01L51/0048 ,  H01L51/0545

Abstract: Transistors with self-aligned source/drain regions and methods for making the same. The methods include forming a gate structure embedded in a recess in a substrate; removing substrate material around the gate structure to create self-aligned source and drain recesses; forming a channel layer over the gate structure and the source and drain recesses; and forming source and drain contacts in the source and drain recesses. The source and drain contacts extend above the channel layer.

Abstract translation: 具有自对准源极/漏极区域的晶体管及其制造方法。 所述方法包括形成嵌入衬底中的凹部中的栅极结构; 去除栅极结构周围的衬底材料以产生自对准的源极和漏极凹槽; 在栅极结构和源极和漏极凹槽上形成沟道层; 以及在源极和漏极凹槽中形成源极和漏极接触。 源极和漏极触点在沟道层上方延伸。

公开(公告)号：US08772100B2

公开(公告)日：2014-07-08

申请号：US13654987

申请日：2012-10-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jingyan Huang ,  Keith Kwong Hon Wong

IPC: H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/51

Abstract: A low gate resistance high-k metal gate transistor device is formed by providing a set of gate stacks (e.g., replacement metal gate (RMG) stacks) in a trench on a silicon substrate. The gate stacks in the trench may have various layers such as: a high-k layer formed over the substrate; a barrier layer (formed over the high-k layer; a p-type work function (pWF) layer formed over the barrier layer; and an n-type work function (nWF) layer formed over the pWF layer. The nWF layer will be subjected to a nitrogen containing plasma treatment to form a nitridized nWF layer on the top surface, and an Al containing layer will then be applied over the gas plasma treated layer. By utilizing a gas plasma treatment, the gap within the trench may remain wider, and thus allow for improved Al fill and reflow at high temperature (400° C.-480° C.) subsequently applied thereto.

Abstract translation: 通过在硅衬底上的沟槽中提供一组栅极堆叠（例如，替换金属栅极（RMG）堆叠）来形成低栅极电阻的高k金属栅极晶体管器件。 沟槽中的栅极堆叠可以具有各种层，例如：在衬底上形成的高k层; 阻挡层（形成在高k层上;形成在势垒层上的p型功函数（pWF）层;以及在pWF层上形成的n型功函数（nWF）层，nWF层将 进行含氮等离子体处理，在顶面形成氮化的nWF层，然后将含Al层施加到气体等离子体处理层上，通过利用气体等离子体处理，沟槽内的间隙保持较宽， 从而允许在随后施加到其上的高温（400℃-480℃）下改善Al填充和回流。

公开(公告)号：US10304735B2

公开(公告)日：2019-05-28

申请号：US15630002

申请日：2017-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Keith Kwong Hon Wong ,  Wonwoo Kim ,  Praneet Adusumilli

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/535 ,  H01L23/485

Abstract: A cobalt contact includes a dual silicide barrier layer. The barrier layer, which may be formed in situ, includes silicides of titanium and cobalt, and provides an effective adhesion layer between the cobalt contact and a conductive device region such as the source/drain junction of a semiconductor device, eliminating void formation during a metal anneal.

公开(公告)号：US10192822B2

公开(公告)日：2019-01-29

申请号：US14623115

申请日：2015-02-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Domingo A. Ferrer ,  Kriteshwar K. Kohli ,  Siddarth A. Krishnan ,  Joseph F. Shepard, Jr. ,  Keith Kwong Hon Wong

IPC: H01L27/112 ,  H01L23/525 ,  H01L23/522 ,  H01L21/768

Abstract: A method for forming a precision resistor or an e-fuse structure where tungsten silicon is used. The tungsten silicon layer is modified by implanting nitrogen into the structure.

公开(公告)号：US20170352619A1

公开(公告)日：2017-12-07

申请号：US15172551

申请日：2016-06-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Baozhen Li ,  Chih-Chao Yang ,  Keith Kwong Hon Wong

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L49/02 ,  H01L23/532 ,  H01L21/02

CPC classification number: H01L23/5223 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L28/60

Abstract: Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming an opening in a low-k dielectric layer; filling the opening with a high-k dielectric material; patterning the low-k dielectric layer outside of the opening and the high-k dielectric layer to form an interconnect opening within the low-k dielectric layer and a capacitor opening within the high-k dielectric layer; and filling the interconnect opening and the capacitor opening with a metal to form an interconnect in the low-k dielectric layer and a capacitor in the high-k dielectric layer.

公开(公告)号：US09343372B1

公开(公告)日：2016-05-17

申请号：US14583835

申请日：2014-12-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruqiang Bao ,  Unoh Kwon ,  Rekha Rajaram ,  Keith Kwong Hon Wong

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/51 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/4966 ,  H01L21/32134 ,  H01L21/823842 ,  H01L29/401 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66606

Abstract: A method includes forming an n-FET device and a p-FET device on a substrate, each of the n-FET device and the p-FET device include a metal gate stack consisting of a titanium-aluminum carbide (TiAlC) layer above and in direct contact with a titanium nitride (TiN) cap, and removing, from the p-FET device, the TiAlC layer selective to the TiN cap. The removal of the TiAlC layer includes using a selective TiAlC to TiN wet etch chemistry solution with a substantially high TiAlC to TiN etch ratio such that the TiN cap remains in the p-FET device.

Abstract translation: 一种方法包括在衬底上形成n-FET器件和p-FET器件，n-FET器件和p-FET器件中的每一个包括由上述钛 - 碳化铝（TiAlC）层和 与氮化钛（TiN）帽直接接触，并且从p-FET器件去除对TiN帽有选择性的TiAlC层。 去除TiAlC层包括使用具有基本上高的TiAlC至TiN蚀刻比的选择性TiAlC至TiN湿蚀刻化学溶液，使得TiN帽保留在p-FET器件中。

公开(公告)号：US20160240478A1

公开(公告)日：2016-08-18

申请号：US14623115

申请日：2015-02-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Domingo A. Ferrer ,  Kriteshwar K. Kohli ,  Siddarth A. Krishnan ,  Joseph F. Shepard, JR. ,  Keith Kwong Hon Wong

IPC: H01L23/525 ,  H01L27/112

CPC classification number: H01L23/5256 ,  H01L21/76886 ,  H01L23/5228 ,  H01L27/11206

Abstract: A method for forming a precision resistor or an e-fuse structure where tungsten silicon is used. The tungsten silicon layer is modified by implanting nitrogen into the structure.

Abstract translation: 用于形成使用钨硅的精密电阻器或e熔丝结构的方法。 通过将氮注入结构来改变钨硅层。

公开(公告)号：US20160240438A1

公开(公告)日：2016-08-18

申请号：US14622997

申请日：2015-02-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicolas L. Breil ,  Domingo A. Ferrer ,  Keith Kwong Hon Wong

IPC: H01L21/768 ,  H01L27/112 ,  H01L23/525

CPC classification number: H01L27/11206 ,  H01L21/76886 ,  H01L23/5228 ,  H01L23/5256 ,  H01L23/53261

Abstract: A method for forming a precision resistor or an e-fuse structure where tungsten silicon is used. The tungsten silicon layer is modified by changing the crystalline structure to a tetragonal tungsten silicon layer.

Abstract translation: 用于形成使用钨硅的精密电阻器或e熔丝结构的方法。 通过将晶体结构改变为四方钨硅层来改变钨硅层。

公开(公告)号：US09335759B2

公开(公告)日：2016-05-10

申请号：US14177260

申请日：2014-02-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicolas L. Breil ,  Oleg Gluschenkov ,  Keith Kwong Hon Wong

IPC: G06F17/50 ,  G05B19/418

CPC classification number: G05B19/41865 ,  G05B2219/32301 ,  G05B2219/45032 ,  H01L21/268 ,  H01L21/324 ,  H01L22/14 ,  H01L22/20 ,  Y02P90/02 ,  Y02P90/20 ,  Y02P90/26

Abstract: Semiconductor chips with curable out of specification measured values of an anneal-activated parameter are identified at a test step. A plurality of anneal plans are generated to include at least one of the identified semiconductor chips. A net yield improvement is calculated for each anneal plan. Each anneal plan includes the paths of a laser beam across the wafer to be irradiated, and optionally includes an azimuthal angle of the wafer as a function of time. The net yield improvement is the difference between an estimated yield improvement from selected target semiconductor chips for irradiation and an estimated yield loss due to collateral irradiation of functional semiconductor chips for each anneal plan. After simulating the net yield improvements for all the anneal plans, the anneal plan providing the greatest net yield improvement can be selected and utilized.

Abstract translation: 在测试步骤中识别具有退火激活参数的规格测量值的可固化的半导体芯片。 生成多个退火计划以包括所识别的半导体芯片中的至少一个。 对每个退火计划计算净产量改进。 每个退火计划包括穿过要照射的晶片的激光束的路径，并且可选地包括作为时间的函数的晶片的方位角。 净收益率的改善是所选择的用于照射的目标半导体芯片的估计产量提高与由于每个退火计划的功能性半导体芯片的侧向照射而导致的估计的产量损失之间的差异。 在模拟所有退火计划的净产量改进之后，可以选择和利用提供最大净产量改进的退火计划。