公开(公告)号：US09425080B2

公开(公告)日：2016-08-23

申请号：US14600229

申请日：2015-01-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Robert H. Dennard ,  Hemanth Jagannathan ,  Ali Khakifirooz ,  Tak H. Ning ,  Ghavam G. Shahidi

IPC: H01L21/762 ,  H01L27/115 ,  B82Y10/00 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L21/76251 ,  B82Y10/00 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11536 ,  H01L27/11543 ,  H01L27/11563 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/7881

Abstract: Semiconductor nanoparticles are deposited on a top surface of a first insulator layer of a substrate. A second insulator layer is deposited over the semiconductor nanoparticles and the first insulator layer. A semiconductor layer is then bonded to the second insulator layer to provide a semiconductor-on-insulator substrate, which includes a buried insulator layer including the first and second insulator layers and embedded semiconductor nanoparticles therein. Back gate electrodes are formed underneath the buried insulator layer, and shallow trench isolation structures are formed to isolate the back gate electrodes. Field effect transistors are formed in a memory device region and a logic device region employing same processing steps. The embedded nanoparticles can be employed as a charge storage element of non-volatile memory devices, in which charge carriers tunnel through the second insulator layer into or out of the semiconductor nanoparticles during writing and erasing.

公开(公告)号：US09356114B2

公开(公告)日：2016-05-31

申请号：US14042951

申请日：2013-10-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kevin K. Chan ,  Bahman Hekmatshoartabari ,  Tak H. Ning ,  Davood Shahrjerdi

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/283 ,  H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L21/308

CPC classification number: H01L29/66242 ,  H01L21/283 ,  H01L21/3086 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/7371

Abstract: A method of forming the heterojunction bipolar transistor that includes providing a stack of a base layer, an extrinsic base layer, a first metal containing layer, and a dielectric cap layer. The dielectric cap layer and the first metal containing layer may be etched to provide a base contact and a dielectric cap. Exposed portions of the base layer may be etched selectively to the dielectric cap. A remaining portion of the base layer provides the base region. A hydrogenated silicon containing layer may be deposited with a low temperature deposition method. At least a portion of the hydrogenated silicon containing layer is formed on at least sidewalls of the base region. A second metal containing layer may be formed on the hydrogenated silicon containing layer. The second metal containing and the hydrogenated silicon containing layer may be etched to provide an emitter region and a collector region.

Abstract translation: 一种形成异质结双极晶体管的方法，其包括提供基底层，非本征基底层，第一金属含量层和电介质盖层的叠层。 可以蚀刻电介质盖层和第一含金属层以提供基极接触和电介质盖。 基底层的暴露部分可以选择性地蚀刻到电介质盖。 基层的剩余部分提供基区。 可以用低温沉积法沉积氢化含硅层。 氢化含硅层的至少一部分形成在基底区域的至少侧壁上。 可以在含氢硅层上形成第二含金属层。 可以蚀刻包含第二金属和含氢硅的层，以提供发射极区域和集电极区域。

公开(公告)号：US09236251B2

公开(公告)日：2016-01-12

申请号：US14705425

申请日：2015-05-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Can Bayram ,  Cheng-Wei Cheng ,  Tak H. Ning ,  Devendra K. Sadana ,  Kuen-Ting Shiu

IPC: H01L21/02 ,  H01L29/267 ,  H01L29/06

CPC classification number: H01L21/0254 ,  H01L21/02365 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02516 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/02664 ,  H01L21/2007 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/267

Abstract: Various methods to integrate a Group III nitride material on a silicon material are provided. In one embodiment, the method includes providing a structure including a (100) silicon layer, a (111) silicon layer located on an uppermost surface of the (100) silicon layer, a Group III nitride material layer located on an uppermost surface of the (111) silicon layer, and a blanket layer of dielectric material located on an uppermost surface of the Group III nitride material layer. Next, an opening is formed through the blanket layer of dielectric material, the Group III nitride material layer, the (111) Si layer and within a portion of the (100) silicon layer. A dielectric spacer is then formed within the opening. An epitaxial semiconductor material is then formed on an exposed surface of the (100) silicon layer within the opening and thereafter planarization is performed.

公开(公告)号：US20170005085A1

公开(公告)日：2017-01-05

申请号：US15264885

申请日：2016-09-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jin Cai ,  Effendi Leobandung ,  Tak H. Ning

IPC: H01L27/06 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L27/092 ,  H01L29/66545

Abstract: A method of forming a semiconductor structure includes depositing a high-k dielectric layer within a first recess located between sidewall spacers of a first CMOS device and within a second recess located between sidewall spacers of a second CMOS device. A dummy titanium nitride layer is deposited on the high-k dielectric layer. Next, the high-k dielectric layer and the dummy titanium nitride layer are removed from the second recess in the second CMOS device. A silicon cap layer is deposited within the first recess and the second recess, the silicon cap layer is located above the high-k dielectric layer and dummy titanium nitride layer in the first CMOS device. Subsequently, dopants are implanted into the silicon cap layer located in the second recess of the second CMOS device.

Abstract translation: 形成半导体结构的方法包括在位于第一CMOS器件的侧壁间隔件之间的第一凹槽内以及位于第二CMOS器件的侧壁间隔物之间​​的第二凹槽内沉积高k电介质层。 在高k电介质层上沉积虚拟氮化钛层。 接下来，从第二CMOS器件的第二凹部去除高k电介质层和虚拟氮化钛层。 在第一凹槽和第二凹槽中沉积硅帽层，硅帽层位于第一CMOS器件中的高k电介质层和虚拟氮化钛层的上方。 随后，将掺杂剂注入到位于第二CMOS器件的第二凹槽中的硅帽层中。

公开(公告)号：US09484430B2

公开(公告)日：2016-11-01

申请号：US14720328

申请日：2015-05-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wilfried E. Haensch ,  Bahman Hekmatshoar-Tabari ,  Ali Khakifirooz ,  Tak H. Ning ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/786 ,  H01L21/02 ,  H01L21/225 ,  H01L29/40 ,  H01L29/417 ,  H01L21/265 ,  H01L29/08

CPC classification number: H01L29/66477 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/2257 ,  H01L21/265 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7841 ,  H01L29/78618 ,  H01L29/78621

Abstract: A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius.

公开(公告)号：US09293454B2

公开(公告)日：2016-03-22

申请号：US14521605

申请日：2014-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jin Cai ,  Tak H. Ning

IPC: H01L27/082 ,  H01L29/423 ,  H01L29/66 ,  H01L29/735 ,  H01L21/8249 ,  H01L29/10 ,  H01L29/45

CPC classification number: H01L27/082 ,  H01L21/8249 ,  H01L29/1004 ,  H01L29/42304 ,  H01L29/45 ,  H01L29/6625 ,  H01L29/735

Abstract: A Bipolar Junction Transistor with an intrinsic base, wherein the intrinsic base includes a top surface and two side walls orthogonal to the top surface, and a base contact electrically coupled to the side walls of the intrinsic base. In one embodiment an apparatus can include a plurality of Bipolar Junction Transistors, and a base contact electrically coupled to the side walls of the intrinsic bases of each BJT.

Abstract translation: 一种具有本征基极的双极结晶体管，其中本征基极包括顶表面和与顶表面正交的两个侧壁，以及电耦合到本征基底的侧壁的基部接触。 在一个实施例中，装置可以包括多个双极结晶体管，以及电耦合到每个BJT的内部基极的侧壁的基部触点。

公开(公告)号：US09240497B2

公开(公告)日：2016-01-19

申请号：US14167499

申请日：2014-01-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Tak H. Ning ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kerber

IPC: H01L21/338 ,  H01L29/812 ,  H01L29/66 ,  H01L29/78 ,  H01L29/808

CPC classification number: H01L29/812 ,  H01L21/84 ,  H01L21/845 ,  H01L27/098 ,  H01L27/1203 ,  H01L29/66545 ,  H01L29/66848 ,  H01L29/66893 ,  H01L29/785 ,  H01L29/808

Abstract: A method of fabricating a semiconductor device that includes forming a replacement gate structure on a portion of a semiconductor substrate, wherein source regions and drain regions are formed in opposing sides of the replacement gate structure. A dielectric is formed on the semiconductor substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the semiconductor substrate. A functional gate conductor is epitaxially grown within the opening in direct contact with the exposed portion of the semiconductor substrate. The method is applicable to planar metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs).