公开(公告)号：US20170250250A1

公开(公告)日：2017-08-31

申请号：US15056966

申请日：2016-02-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven Bentley ,  Deepak Nayak

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/165 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02236 ,  H01L21/02532 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor structure, comprising a semiconductor substrate; at least one fin, wherein the at least one fin comprises one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers; a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, and an epitaxial source/drain material disposed on at least the exposed portions of each of the first layers. Methods and systems for forming the semiconductor structure.

公开(公告)号：US10396121B2

公开(公告)日：2019-08-27

申请号：US15680948

申请日：2017-08-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey P. Jacob ,  Srinivasa Banna ,  Deepak Nayak

IPC: H01L27/15 ,  H01L33/06 ,  H01L33/24 ,  H01L33/00 ,  H01L33/32 ,  H01L33/60 ,  H01L33/50 ,  H01L29/78

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs for light emitting diode displays and methods of manufacture. The method includes: forming replacement fin structures with a doped core region, on doped substrate material; forming quantum wells over the replacement fin structures; forming a first color emitting region by doping at least one of the quantum wells over at least a first replacement fin structure of the replacement fin structures, while protecting at least a second replacement fin structure of the replacement fin structures; and forming a second color emitting region by doping another one of the quantum wells over the at least second replacement fin structure of the replacement fin structures, while protecting the first replacement fin structure and other replacement fin structures which are not to be doped.

公开(公告)号：US10283560B2

公开(公告)日：2019-05-07

申请号：US15899374

申请日：2018-02-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Deepak Nayak ,  Srinivasa Banna ,  Ajey P. Jacob

IPC: H01L27/15 ,  H01L33/06 ,  H01L33/24 ,  H01L23/48 ,  H01L33/00

Abstract: Disclosed is a device which includes first and second major substrate surfaces. The first substrate surface includes an LED with first and second terminals while the second substrate surface includes CMOS circuit components. The CMOS components and LED are coupled by through silicon via (TSV) contacts which extend through the second substrate surface.

公开(公告)号：US10193011B1

公开(公告)日：2019-01-29

申请号：US15650427

申请日：2017-07-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Srinivasa Banna ,  Deepak Nayak ,  Luke England ,  Rahul Agarwal

IPC: H01L27/30 ,  H01L31/18 ,  H01L27/15

Abstract: Methods of forming an integrated RGB LED and Si CMOS driver wafer and the resulting devices are provided. Embodiments include providing a plurality of first color die over a CMOS wafer, each first color die being laterally separated with a first oxide and electrically connected to the CMOS wafer; providing a second color die above each first color die, each second color die being separated from each other with a second oxide, bonded to a first color die, and electrically connected to the CMOS wafer through the bonded first color die; removing a portion of each second color die to expose a portion of each bonded first color die; forming a conformal TCO layer over each first and second color die and on a side surface of each second color die and oxide; forming a PECVD oxide layer over the CMOS wafer; and planarizing the PECVD oxide layer.

公开(公告)号：US09941330B2

公开(公告)日：2018-04-10

申请号：US15599458

申请日：2017-05-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Srinivasa Banna ,  Deepak Nayak ,  Ajey P. Jacob

IPC: H01L21/00 ,  H01L27/15 ,  H01L33/06 ,  H01L33/16 ,  H01L33/32 ,  H01L33/12 ,  H01L33/62 ,  H01L33/20 ,  H01L33/00

CPC classification number: H01L27/156 ,  H01L33/0025 ,  H01L33/007 ,  H01L33/06 ,  H01L33/12 ,  H01L33/16 ,  H01L33/20 ,  H01L33/24 ,  H01L33/32 ,  H01L33/62 ,  H01L2933/0066

Abstract: Devices and methods of forming the devices are disclosed. The device includes a substrate and a color LED pixel disposed on the substrate. The color LED pixel includes a red LED, a green LED and a blue LED. Each of the color LED includes a specific color LED body disposed on the respective color region on the substrate, a specific color multiple quantum well (MQW) on the respective color LED body and a specific color top LED layer disposed over the respective color MQW. The MQWs of the red LED, green LED and blue LED includes at least an indium gallium nitride (InxGa1−xN) layer and a gallium nitride (GaN), where x is the atomic percentage of In in the InxGa1−xN layer, and the MQWs of the red LED, green LED and blue LED have different bandgaps by varying x of the InxGa1−xN layer in the red LED, the green LED and the blue LED.

公开(公告)号：US09941329B2

公开(公告)日：2018-04-10

申请号：US15599438

申请日：2017-05-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Deepak Nayak ,  Srinivasa Banna ,  Ajey P. Jacob

IPC: H01L21/00 ,  H01L27/15 ,  H01L33/06 ,  H01L33/00 ,  H01L33/24 ,  H01L23/48

CPC classification number: H01L27/156 ,  H01L23/481 ,  H01L33/0029 ,  H01L33/06 ,  H01L33/24 ,  H01L2933/0066

Abstract: Disclosed is a multi-color semiconductor LED display with integrated with CMOS circuit components, such as thin film transistors (TFTs). LEDs of the display are disposed on a first major surface of a substrate while CMOS circuit components which are configured as circuitry for operating the display are disposed on a second opposing major surface of the substrate. The CMOS components and LEDs are coupled by through silicon via (TSV) contacts through the substrate. Integrating CMOS components with LED on one substrate enhances compactness of the display. Other advantages include low power and low cost with high brightness and resolution desired for portable applications, including virtual reality and augmented reality applications.

公开(公告)号：US09748335B1

公开(公告)日：2017-08-29

申请号：US15056966

申请日：2016-02-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven Bentley ,  Deepak Nayak

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02236 ,  H01L21/02532 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor structure, comprising a semiconductor substrate; at least one fin, wherein the at least one fin comprises one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers; a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, and an epitaxial source/drain material disposed on at least the exposed portions of each of the first layers. Methods and systems for forming the semiconductor structure.

公开(公告)号：US09711511B1

公开(公告)日：2017-07-18

申请号：US15193867

申请日：2016-06-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwan-Yong Lim ,  Ryan Ryoung-Han Kim ,  Motoi Ichihashi ,  Youngtag Woo ,  Deepak Nayak

IPC: H01L29/66 ,  H01L27/11 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L27/1104 ,  H01L29/1037 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/513 ,  H01L29/7827

Abstract: A semiconductor memory structure (e.g., SRAM) includes vertical channels with a circular, square or rectangular cross-sectional shape. Each unit cell can include a single pull-up vertical transistor and either: one pull-down vertical transistor and one pass-gate vertical transistor; or two or more of each of the pull-down and pass-gate vertical transistors. The structure may be realized by providing adjacent layers of undoped semiconductor material, forming vertical channels for vertical transistors, the vertical channels situated on each of the adjacent layers, doping a first half of each of the adjacent layers with a n-type or p-type dopant, doping a second half of each of the adjacent layers with an opposite type dopant to that of the first half, forming wrap-around gates surrounding the vertical channels, and forming top electrodes for the vertical transistors.

公开(公告)号：US09685529B1

公开(公告)日：2017-06-20

申请号：US15189476

申请日：2016-06-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Deepak Nayak ,  Zoran Krivokapic ,  Srinivasa Banna

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/532

CPC classification number: H01L29/66522 ,  H01L21/76867 ,  H01L23/53271 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods for creating barrier layers in a III-V electron channel to reduce band-to-band leakage current and the resulting devices are disclosed. Embodiments include forming a fin channel portion comprising a III-V material, on a barrier layer; forming undoped InP semiconductor spacers at opposite ends of the fin channel portion on the barrier layer; forming S/D regions adjacent the undoped InP semiconductor spacers on the barrier layer; and forming a high-k/metal gate over the fin channel portion and undoped InP semiconductor spacers.