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    Diodes and fabrication methods thereof
    11.
    发明授权
    Diodes and fabrication methods thereof 有权

    公开(公告)号：US09768325B2

    公开(公告)日：2017-09-19

    申请号：US14730294

    申请日：2015-06-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Min-hwa Chi

    IPC: H01L29/866 ,  H01L21/306 ,  H01L29/66 ,  H01L29/06 ,  H01L29/165

    CPC classification number: H01L29/866 ,  H01L21/306 ,  H01L29/0684 ,  H01L29/0688 ,  H01L29/165 ,  H01L29/66106

    Abstract: Diodes and fabrication methods thereof are presented. The diodes include, for instance: a first semiconductor region disposed at least partially within a substrate, the first semiconductor region having a first conductivity type; and a second semiconductor region disposed at least partially within the first semiconductor region, the second semiconductor region having a second conductivity type, wherein the first semiconductor region separates the second semiconductor region from the substrate. In one embodiment, the substrate and the first semiconductor region have a sigma-shaped boundary. In another embodiment, the substrate and the first semiconductor region have U-shaped boundary. In a further embodiment, the first semiconductor region comprises an alloy of a first material and a second material, where the concentration of the second material varies from a maximum to a minimum, where the first semiconductor region adjacent to the second semiconductor region has the minimum of the concentration of the second material.

    Fin structures and multi-Vt scheme based on tapered fin and method to form
    14.
    发明授权
    Fin structures and multi-Vt scheme based on tapered fin and method to form 有权
    翅片结构和多Vt方案基于锥形翅片和方法形成

    公开(公告)号：US09583625B2

    公开(公告)日：2017-02-28

    申请号：US14523548

    申请日：2014-10-24

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Xusheng Wu ,  Min-hwa Chi ,  Edmund Kenneth Banghart

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

    CPC classification number: H01L29/66537 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/7853

    Abstract: A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt schemes and the resulting device are provided. Embodiments include forming an Si fin, the Si fin having a top active portion and a bottom active portion; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal the active top portion of the Si fin; etching the top active portion of the Si fin to form vertical sidewalls; forming a nitride spacer covering each vertical sidewall; recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; and tapering the active bottom portion of the Si fin.

    Abstract translation: 提供一种形成具有低掺杂和高掺杂有源部分的FinFET鳍片的方法和/或具有用于Vt调谐和多Vt方案的锥形侧壁的FinFET鳍片以及所得到的器件。 实施例包括形成Si翅片，所述Si翅片具有顶部活性部分和底部活性部分; 在Si翅片的顶表面上形成硬掩模; 在所述Si翅片的相对侧上形成氧化物层; 将掺杂剂注入到Si鳍中; 凹陷氧化物层以露出Si鳍的有效顶部; 蚀刻Si翅片的顶部活性部分以形成垂直侧壁; 形成覆盖每个垂直侧壁的氮化物间隔物; 凹陷凹陷的氧化物层以露出Si鳍的活性底部; 并使Si翅片的活性底部部分变细。

    Fabricating transistors having resurfaced source/drain regions with stressed portions
    15.
    发明授权
    Fabricating transistors having resurfaced source/drain regions with stressed portions 有权
    制造具有应力部分的具有重新覆盖的源极/漏极区域的晶体管

    公开(公告)号：US09559166B2

    公开(公告)日：2017-01-31

    申请号：US14609504

    申请日：2015-01-30

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Shishir Ray ,  Bharat Krishnan ,  Min-hwa Chi

    IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/324 ,  H01L29/04 ,  H01L21/268

    CPC classification number: H01L29/0847 ,  H01L21/268 ,  H01L21/3247 ,  H01L29/045 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7847 ,  H01L29/7848

    Abstract: Methods are providing for fabricating transistors having at least one source region or drain region with a stressed portion. The methods include: forming, within a cavity of a substrate structure, the at least one source region or drain region with the internal stress; and resurfacing the at least one source region or drain region to reduce surface defects of the at least one source region or drain region without relaxing the stressed portion thereof. For instance, the resurfacing can include melting an upper portion of the at least one source region or drain region. In addition, the resurfacing can include re-crystallizing an upper portion of the at least one source region or drain region, and/or providing the at least one source region or drain region with at least one {111} surface.

    Abstract translation: 提供制造具有至少一个具有应力部分的源极区或漏极区的晶体管的方法。 所述方法包括：在衬底结构的空腔内形成具有内部应力的至少一个源极区域或漏极区域; 以及重新铺展所述至少一个源极区域或漏极区域以减少所述至少一个源极区域或漏极区域的表面缺陷，而不放松其应力部分。 例如，表面重排可以包括熔化至少一个源区或漏区的上部。 另外，重新表面可以包括重新结晶至少一个源区或漏区的上部，和/或向至少一个源区或漏区提供至少一个{111}表面。

    Shallow trench isolation structure with sigma cavity
    16.
    发明授权
    Shallow trench isolation structure with sigma cavity 有权
    浅沟槽隔离结构，带有Σ腔

    公开(公告)号：US09548357B2

    公开(公告)日：2017-01-17

    申请号：US14716696

    申请日：2015-05-19

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： HaoCheng Tsai ,  Min-hwa Chi

    IPC: H01L21/762 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3065

    CPC classification number: H01L29/0653 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/76232 ,  H01L29/66568 ,  H01L29/66636 ,  H01L29/7846 ,  H01L29/7848

    Abstract: Embodiments of the present invention provide an improved shallow trench isolation structure and method of fabrication. The shallow trench isolation cavity includes an upper region having a sigma cavity shape, and a lower region having a substantially rectangular cross-section. The lower region is filled with a first material having good gap fill properties. The sigma cavity is filled with a second material having good stress-inducing properties. In some embodiments, source/drain stressor cavities may be eliminated, with the stress provided by the shallow trench isolation structure. In other embodiments, the stress from the shallow trench isolation structure may be used to complement or counteract stress from a source/drain stressor region of an adjacent transistor. This enables precise tuning of channel stress to achieve a desired carrier mobility for a transistor.

    Abstract translation: 本发明的实施例提供了一种改进的浅沟槽隔离结构和制造方法。 浅沟槽隔离腔包括具有西格玛腔形状的上部区域和具有基本矩形横截面的下部区域。 下部区域填充有具有良好间隙填充性能的第一材料。 西格玛腔填充有具有良好的应力诱导性能的第二材料。 在一些实施例中，可以消除源极/漏极应力源空穴，同时由浅沟槽隔离结构提供的应力。 在其他实施例中，来自浅沟槽隔离结构的应力可以用于补偿或抵消来自相邻晶体管的源极/漏极应力区域的应力。 这使得能够精确地调谐通道应力以实现晶体管的期望的载流子迁移率。

    FINFET DEVICES HAVING ASYMMETRICAL EPITAXIALLY-GROWN SOURCE AND DRAIN REGIONS AND METHODS OF FORMING THE SAME
    17.
    发明申请
    FINFET DEVICES HAVING ASYMMETRICAL EPITAXIALLY-GROWN SOURCE AND DRAIN REGIONS AND METHODS OF FORMING THE SAME 审中-公开
    具有非对称外延源和漏区的FINFET器件及其形成方法

    公开(公告)号：US20160315172A1

    公开(公告)日：2016-10-27

    申请号：US14695411

    申请日：2015-04-24

    Applicant: GLOBALFOUNDRIES, INC.

    Inventor： Xusheng Wu ,  Changyong Xiao ,  Min-hwa Chi

    IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L29/08

    CPC classification number: H01L29/7848 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66795

    Abstract: Fin field-effect transistor (FinFET) devices and methods of forming the same are provided herein. In an embodiment, a FinFET device includes a semiconductor substrate having a plurality of fins disposed in parallel relationship. A first insulator layer overlies the semiconductor substrate, with the fins extending through and protruding beyond the first insulator layer to provide exposed fin portions. A gate electrode structure overlies the exposed fin portions and is electrically insulated from the fins by a gate insulating layer. Epitaxially-grown source regions and drain regions are disposed adjacent to the gate electrode structure. The epitaxially-grown source regions and drain regions have an asymmetric profile along a lateral direction perpendicular to a length of the fins.

    Abstract translation: Fin场效应晶体管（FinFET）器件及其形成方法在此提供。 在一个实施例中，FinFET器件包括具有平行关系设置的多个鳍片的半导体衬底。 第一绝缘体层覆盖在半导体衬底上，鳍片延伸穿过第一绝缘体层并突出超过第一绝缘体层以提供暴露的鳍部分。 栅电极结构覆盖在暴露的鳍部上，并通过栅极绝缘层与散热片电绝缘。 外延生长的源极区域和漏极区域邻近栅电极结构设置。 外延生长的源极区域和漏极区域沿着垂直于鳍片的长度的横向方向具有不对称轮廓。

    Methods of manufacturing integrated circuits having FinFET structures with epitaxially formed source/drain regions
    19.
    发明授权
    Methods of manufacturing integrated circuits having FinFET structures with epitaxially formed source/drain regions 有权
    制造具有外延形成的源/漏区的FinFET结构的集成电路的方法

    公开(公告)号：US09153496B2

    公开(公告)日：2015-10-06

    申请号：US14570049

    申请日：2014-12-15

    Applicant: GLOBALFOUNDRIES, INC.

    Inventor： Hoong Shing Wong ,  Min-hwa Chi

    IPC: H01L21/8234 ,  H01L21/336 ,  H01L21/8238

    CPC classification number: H01L21/823418 ,  H01L21/823431 ,  H01L21/823821

    Abstract: Methods of manufacturing semiconductor integrated circuits having FinFET structures with epitaxially formed source and drain regions are disclosed. A method of fabricating an integrated circuit includes forming a plurality of silicon fin structures on a semiconductor substrate, epitaxially growing a silicon material on the fin structures, wherein a merged source/drain region is formed on the fin structures, and anisotropically etching at least one of the merged source drain regions to form an un-merged source/drain region.

    Abstract translation: 公开了具有外延形成的源极和漏极区域的FinFET结构的半导体集成电路的制造方法。 一种制造集成电路的方法包括在半导体衬底上形成多个硅鳍结构，在翅片结构上外延生长硅材料，其中在翅片结构上形成合并的源极/漏极区，并且各向异性地蚀刻至少一个 的合并源极漏极区域以形成未合并的源极/漏极区域。

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