公开(公告)号：US09269666B2

公开(公告)日：2016-02-23

申请号：US14158904

申请日：2014-01-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

IPC: H01L23/528 ,  H01L21/3105 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/31056 ,  H01L21/76819 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer on a top surface of multiple conductive features and on a top surface of a substrate between the conductive features. A portion of the first dielectric layer is selectively removed from the top surface of at least one of the conductive features without removing a portion the first dielectric layer that is between the conductive features. A second dielectric layer is formed on the top surface of the at least one of the conductive features and on a top surface of the first dielectric layer, and a top surface of the second dielectric layer is planarized. A layer operating as an etch stop is located between the top surface of at least one of the conductive features and the second dielectric layer.

Abstract translation: 用于平坦化诸如电介质的材料层的平面化方法以及通过平面化方法形成的互连结构。 该方法包括在多个导电特征的顶表面和导电特征之间的衬底的顶表面上沉积第一介电层。 第一介电层的一部分从至少一个导电特征的顶表面选择性地去除，而不去除导电特征之间的第一介电层的一部分。 第二电介质层形成在至少一个导电特征的顶表面上和第一介电层的顶表面上，并且第二介电层的顶表面被平坦化。 作为蚀刻停止件操作的层位于导电特征中的至少一个的顶表面和第二介电层之间。

公开(公告)号：US10224276B2

公开(公告)日：2019-03-05

申请号：US15787146

申请日：2017-10-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Robert K. Leidy

IPC: H01L29/40 ,  H01L23/522 ,  H01L23/525 ,  H01L23/532 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31

Abstract: Various aspects include an integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via.

公开(公告)号：US20170330832A1

公开(公告)日：2017-11-16

申请号：US15152794

申请日：2016-05-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhong-Xiang He ,  Mark D. Jaffe ,  Randy L. Wolf ,  Alvin J. Joseph ,  Brett T. Cucci ,  Anthony K. Stamper

IPC: H01L23/522 ,  H01L23/66 ,  H01L23/528 ,  H01L27/12

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L23/4821 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/1203

Abstract: A semiconductor device may include a transistor gate in a device layer; an interconnect layer over the device layer; and an air gap extending through the interconnect layer to contact an upper surface of the transistor gate. The air gap provides a mechanism to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches.

公开(公告)号：US09703036B2

公开(公告)日：2017-07-11

申请号：US15041103

申请日：2016-02-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhong-Xiang He ,  Qizhi Liu ,  Ronald G. Meunier ,  Steven M. Shank

IPC: G02B6/12 ,  G02B6/42 ,  G02B6/122 ,  G02B6/136 ,  G02B6/132

CPC classification number: G02B6/12002 ,  G02B6/122 ,  G02B6/132 ,  G02B6/136 ,  G02B6/42 ,  G02B2006/121 ,  G02B2006/12119

Abstract: Disclosed are structures with an optical waveguide having a first segment at a first level and a second segment extending between the first level and a higher second level and further extending along the second level. Specifically, the waveguide comprises a first segment between first and second dielectric layers. The second dielectric layer has a trench, which extends through to the first dielectric layer and which has one side positioned laterally adjacent to an end of the first segment. The waveguide also comprises a second segment extending from the bottom of the trench on the side adjacent to the first segment up to and along the top surface of the second dielectric layer on the opposite side of the trench. A third dielectric layer covers the second segment in the trench and on the top surface of the second dielectric layer. Also disclosed are methods of forming such optoelectronic structures.

公开(公告)号：US20160111352A1

公开(公告)日：2016-04-21

申请号：US14967965

申请日：2015-12-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Daniel J. Couture ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Anthony K. Stamper

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/3212 ,  H01L21/76816 ,  H01L21/76834 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02125 ,  H01L2224/0226 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/05442

Abstract: An approach to creating a semiconductor structure for a dielectric layer over a void area includes determining a location of a void area of the topographical semiconductor feature. A second dielectric layer is deposited on a first dielectric layer and a top surface of a topographical semiconductor feature. The second dielectric layer is patterned to one or more portions, wherein at least one portion of the patterned second dielectric layer is over the location of the void area of the topographical semiconductor feature. A first metal layer is deposited over the second dielectric layer, at least one portion of the first dielectric layer, and a portion of the top surface of the topographical semiconductor feature. A chemical mechanical polish of the first metal layer is performed, wherein the chemical mechanical polish reaches the top surface of at least one of the one or more portions of the second dielectric layer.

Abstract translation: 在空隙区域上形成用于介电层的半导体结构的方法包括确定形貌半导体特征的空隙区域的位置。 第二电介质层沉积在第一介电层和地形半导体特征的顶表面上。 将第二介电层图案化成一个或多个部分，其中图案化的第二介电层的至少一部分在形貌半导体特征的空隙区域的位置之上。 第一金属层沉积在第二电介质层上，第一介电层的至少一部分和形貌半导体特征的顶表面的一部分。 执行第一金属层的化学机械抛光，其中化学机械抛光剂到达第二介电层的一个或多个部分中的至少一个的顶表面。

公开(公告)号：US10157777B2

公开(公告)日：2018-12-18

申请号：US15152797

申请日：2016-05-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhong-Xiang He ,  Mark D. Jaffe ,  Randy L. Wolf ,  Alvin J. Joseph ,  Brett T. Cucci ,  Anthony K. Stamper

IPC: H01L29/00 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/84 ,  H01L23/66 ,  H01L29/786

Abstract: A semiconductor device may include a transistor gate in a device layer; an interconnect layer over the device layer; and an air gap extending through the interconnect layer to contact an upper surface of the transistor gate. The air gap provides a mechanism to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches.