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    Method and device for reducing contamination for reliable bond pads
    12.
    发明授权
    Method and device for reducing contamination for reliable bond pads 有权

    公开(公告)号：US10410854B2

    公开(公告)日：2019-09-10

    申请号：US15857546

    申请日：2017-12-28

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Honghui Mou ,  Xiaodong Li ,  Yun Ling Tan ,  Alex See ,  Liang Li

    IPC: H01L21/02 ,  H01L21/60

    Abstract: The present disclosure generally relates to methods for cleaning the backside of a wafer. A wet cleaning method may be used by stripping off the uppermost spacer layers on the backside of the wafer using a cleaning solution. In one embodiment, hydrogen fluoride (HF) solution may be employed to remove the nitride/oxide spacer layer. In another embodiment, a dry cleaning method may be employed to etch the wafer at the bevel region. Residues are completely removed from the wafer backside. This method improves the yield and storage life of the semiconductor wafers.

    Methods for removal of hard mask
    13.
    发明授权
    Methods for removal of hard mask 有权

    公开(公告)号：US10115625B2

    公开(公告)日：2018-10-30

    申请号：US15394851

    申请日：2016-12-30

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Liang Li ,  Yun Ling Tan ,  Hai Cong ,  Changwei Pei ,  Alex See

    IPC: H01L21/762 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3065 ,  H01L27/11548 ,  H01L27/11575

    Abstract: Embodiments of a method of processing semiconductor devices are presented. The method includes providing a substrate prepared with isolation regions having a non-planar surface topology. The substrate includes at least first and second regions. The first region includes a memory region and the second region includes a logic region. A hard mask layer is formed covering the substrate and the isolation regions with non-planar surface topology. The method includes selectively processing an exposed portion of the hard mask layer over a select region while protecting a portion of the hard mask layer over a non-select region. The top substrate area and isolation regions of the non-select region are not exposed during processing of the portion of the hard mask layer over the select region. Hard mask residue is completely removed over the select region during processing of the exposed portion of the hard mask layer.

    CD control
    14.
    发明授权
    CD control 有权

    公开(公告)号：US10103097B2

    公开(公告)日：2018-10-16

    申请号：US14484220

    申请日：2014-09-11

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Zheng Zou ,  Alex See ,  Huang Liu ,  Hai Cong

    IPC: H01L21/302 ,  H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L21/311

    Abstract: A method includes providing a substrate with a patterned second layer over a first layer. The second layer includes a second layer opening having a first CD equal to the CD produced by a lithographic system (CDL). CDL is larger than a desired CD (CDD). A third layer is formed to fill the opening, leaving a top surface of the second layer exposed. The second layer is removed to produce a mesa formed by the third layer. The CD of the mesa is equal to about the first CD. The mesa is trimmed to produce a mesa with a second CD equal to about CDD. A fourth layer is formed to cover the first layer, leaving a top of the mesa exposed. The substrate is etched to remove the mesa and a portion of the first layer below the mesa to form an opening in the first layer with CDD.

    Isolation for embedded devices
    18.
    发明授权
    Isolation for embedded devices 有权
    嵌入式设备的隔离

    公开(公告)号：US09349654B2

    公开(公告)日：2016-05-24

    申请号：US14228258

    申请日：2014-03-28

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Liang Li ,  Xuesong Rao ,  Martina Damayanti ,  Wei Lu ,  Alex See ,  Yoke Leng Lim

    IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/28 ,  H01L29/06 ,  H01L21/762 ,  H01L27/115

    CPC classification number: H01L21/823481 ,  H01L21/28229 ,  H01L21/28273 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/762 ,  H01L21/76224 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/0649

    Abstract: Device and a method of forming a device are presented. The method includes providing a substrate prepared with isolation regions. The substrate includes first, second and third regions. The first region includes a memory region, the second region includes a high voltage (HV) region and the third region includes a logic region. An additional dielectric layer covering the substrate and the isolation regions is formed. A first select region is selectively processed while protecting first non-select regions. The first select region is one of the first, second and third device regions. A first gate dielectric is formed on the select region. Top substrate active area and isolation regions of the first non-select regions are not exposed during processing of the first select region and forming the first gate dielectric.

    Abstract translation: 介绍了器件和形成器件的方法。 该方法包括提供用隔离区制备的底物。 衬底包括第一，第二和第三区域。 第一区域包括存储区域，第二区域包括高电压（HV）区域，第三区域包括逻辑区域。 形成覆盖基板和隔离区域的附加电介质层。 选择性地处理第一选择区域，同时保护第一非选择区域。 第一选择区域是第一，第二和第三设备区域之一。 在选择区域上形成第一栅极电介质。 第一非选择区域的顶部衬底有源面积和隔离区域在第一选择区域的处理期间不暴露并形成第一栅极电介质。

    THROUGH SILICON VIAS
    19.
    发明申请
    THROUGH SILICON VIAS 有权
    通过硅胶

    公开(公告)号：US20140264911A1

    公开(公告)日：2014-09-18

    申请号：US13831898

    申请日：2013-03-15

    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.

    Inventor： Benfu LIN ,  Hong Yu ,  Lup San ,  Alex See ,  Wei Lu

    IPC: H01L23/48 ,  H01L21/768

    CPC classification number: H01L23/535 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface.

    Abstract translation: 公开了一种用于形成装置的装置和方法。 提供衬底，并且通过衬底的顶表面在衬底中形成TSV。 衬底的TSV和顶表面衬有具有第一绝缘层，抛光停止层和第二绝缘层的绝缘堆叠。 在基板上形成导电层。 TSV填充有导电层的导电材料。 将衬底平坦化以除去导电层的过量导电材料。 平坦化停止在抛光停止层上以形成平坦的顶表面。

    CMP head structure with retaining ring
    20.
    发明授权
    CMP head structure with retaining ring 有权
    CMP头结构带保持环

    公开(公告)号：US09511470B2

    公开(公告)日：2016-12-06

    申请号：US15005034

    申请日：2016-01-25

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Benfu Lin ,  Lei Wang ,  Xuesong Rao ,  Wei Lu ,  Alex See

    IPC: B24B37/005 ,  B24B49/16 ,  B24B37/32

    CPC classification number: B24B37/005 ,  B24B37/32 ,  B24B49/16

    Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table, a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes a retaining ring, a sensor for sensing the depth of grooves on the retaining ring and a controller for determining an update pressure to apply to the retaining ring based on the depth of the grooves and applying the updated pressure to the retaining ring during processing.

    Abstract translation: 提出了一种用于CMP处理的CMP结构和使用其的装置的制造方法。 该装置包括在压板台上的抛光垫，用于将晶片保持在抛光垫上的头组件，其中头部组件包括保持环，用于感测保持环上的凹槽的深度的传感器，以及用于确定 基于槽的深度更新施加到保持环的压力，并且在处理期间将更新的压力施加到保持环。

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