公开(公告)号：US09511470B2

公开(公告)日：2016-12-06

申请号：US15005034

申请日：2016-01-25

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Benfu Lin ,  Lei Wang ,  Xuesong Rao ,  Wei Lu ,  Alex See

IPC: B24B37/005 ,  B24B49/16 ,  B24B37/32

CPC classification number: B24B37/005 ,  B24B37/32 ,  B24B49/16

Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table, a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes a retaining ring, a sensor for sensing the depth of grooves on the retaining ring and a controller for determining an update pressure to apply to the retaining ring based on the depth of the grooves and applying the updated pressure to the retaining ring during processing.

Abstract translation: 提出了一种用于CMP处理的CMP结构和使用其的装置的制造方法。 该装置包括在压板台上的抛光垫，用于将晶片保持在抛光垫上的头组件，其中头部组件包括保持环，用于感测保持环上的凹槽的深度的传感器，以及用于确定 基于槽的深度更新施加到保持环的压力，并且在处理期间将更新的压力施加到保持环。

公开(公告)号：US09242341B2

公开(公告)日：2016-01-26

申请号：US14059451

申请日：2013-10-22

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Benfu Lin ,  Wei Lu ,  Alex See

IPC: B24B49/00 ,  B24B37/005 ,  B24B37/32

CPC classification number: B24B49/00 ,  B24B37/005 ,  B24B37/32

Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table; a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes the retaining ring; a sensor for sensing the step height between the retaining ring and its membrane and a controller for adjusting the movement of the retaining ring based on the step height between the retaining ring and its membrane to ensure the step height remains at a fixed value as the retaining ring wears out.

Abstract translation: 提出了一种用于CMP处理的CMP结构和使用其的装置的制造方法。 该装置包括在台板上的抛光垫; 用于将晶片保持在抛光垫上的头组件，其中所述头组件包括所述保持环; 用于感测保持环和其膜之间的台阶高度的传感器和用于根据保持环与其膜之间的台阶高度来调节保持环的运动的控制器，以确保台阶高度保持在固定值，作为保持 戒指磨损了。

公开(公告)号：US09153473B2

公开(公告)日：2015-10-06

申请号：US14032206

申请日：2013-09-20

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Liang Li ,  Wei Lu

IPC: H01L21/311 ,  H01L21/336 ,  H01L21/461 ,  H01L21/76 ,  H01L23/58 ,  H01L21/762 ,  H01L21/3213

CPC classification number: H04N5/33 ,  G06K9/00335 ,  G06T7/20 ,  H01L21/0209 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/76224 ,  H01L27/14649 ,  H04N5/35572 ,  H04N5/3575 ,  H04N5/365 ,  H04N5/3698 ,  H04N5/374 ,  H04N5/378

Abstract: Methods for forming a device are presented. A substrate having top and bottom pad stacks is provided. Each pad stack includes at least first and second pad layers. The second pad layers of the top and bottom pad stacks include an initial thickness TT1 and TB1 respectively. Trench isolation regions are formed in the substrate. The second pad layer of the top and bottom pad stacks are removed after forming the trench isolation regions by a batch wet etch process.

Abstract translation: 提出了形成装置的方法。 提供了具有顶部和底部垫堆叠的基板。 每个垫堆叠包括至少第一和第二垫层。 顶部和底部垫堆叠的第二垫层分别包括初始厚度TT1和TB1。 在衬底中形成沟槽隔离区。 在通过分批湿式蚀刻工艺形成沟槽隔离区域之后，去除顶部和底部焊盘堆叠的第二焊盘层。

公开(公告)号：US20150187641A1

公开(公告)日：2015-07-02

申请号：US14145581

申请日：2013-12-31

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Lei Wang ,  Lup San Leong ,  Wei Lu ,  Alex See

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/02

CPC classification number: H01L21/76819 ,  H01L21/02164 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/76805 ,  H01L21/76837 ,  H01L21/76879 ,  H01L23/3192 ,  H01L23/485 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits with reduced shorting and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes depositing a gap fill dielectric overlying a semiconductor substrate. The gap fill dielectric is formed with an upper surface having a height differential. The method includes reducing the height differential of the upper surface of the gap fill dielectric. Further, the method includes depositing an interlayer dielectric overlying the gap fill dielectric. Also, the method forms an electrical contact to a selected location overlying the semiconductor substrate.

Abstract translation: 提供具有减少短路的集成电路和制造这种集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括沉积覆盖半导体衬底的间隙填充电介质。 间隙填充电介质形成有具有高度差的上表面。 该方法包括减小间隙填充电介质的上表面的高度差。 此外，该方法包括沉积覆盖间隙填充电介质的层间电介质。 此外，该方法形成与覆盖半导体衬底的选定位置的电接触。

公开(公告)号：US09349654B2

公开(公告)日：2016-05-24

申请号：US14228258

申请日：2014-03-28

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Liang Li ,  Xuesong Rao ,  Martina Damayanti ,  Wei Lu ,  Alex See ,  Yoke Leng Lim

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/28 ,  H01L29/06 ,  H01L21/762 ,  H01L27/115

CPC classification number: H01L21/823481 ,  H01L21/28229 ,  H01L21/28273 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/762 ,  H01L21/76224 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/0649

Abstract: Device and a method of forming a device are presented. The method includes providing a substrate prepared with isolation regions. The substrate includes first, second and third regions. The first region includes a memory region, the second region includes a high voltage (HV) region and the third region includes a logic region. An additional dielectric layer covering the substrate and the isolation regions is formed. A first select region is selectively processed while protecting first non-select regions. The first select region is one of the first, second and third device regions. A first gate dielectric is formed on the select region. Top substrate active area and isolation regions of the first non-select regions are not exposed during processing of the first select region and forming the first gate dielectric.

Abstract translation: 介绍了器件和形成器件的方法。 该方法包括提供用隔离区制备的底物。 衬底包括第一，第二和第三区域。 第一区域包括存储区域，第二区域包括高电压（HV）区域，第三区域包括逻辑区域。 形成覆盖基板和隔离区域的附加电介质层。 选择性地处理第一选择区域，同时保护第一非选择区域。 第一选择区域是第一，第二和第三设备区域之一。 在选择区域上形成第一栅极电介质。 第一非选择区域的顶部衬底有源面积和隔离区域在第一选择区域的处理期间不暴露并形成第一栅极电介质。

公开(公告)号：US20140264911A1

公开(公告)日：2014-09-18

申请号：US13831898

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.

Inventor： Benfu LIN ,  Hong Yu ,  Lup San ,  Alex See ,  Wei Lu

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface.

Abstract translation: 公开了一种用于形成装置的装置和方法。 提供衬底，并且通过衬底的顶表面在衬底中形成TSV。 衬底的TSV和顶表面衬有具有第一绝缘层，抛光停止层和第二绝缘层的绝缘堆叠。 在基板上形成导电层。 TSV填充有导电层的导电材料。 将衬底平坦化以除去导电层的过量导电材料。 平坦化停止在抛光停止层上以形成平坦的顶表面。

公开(公告)号：US09520371B2

公开(公告)日：2016-12-13

申请号：US14525154

申请日：2014-10-27

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Benfu Lin ,  Wanbing Yi ,  Wei Lu ,  Alex See ,  Juan Boon Tan

IPC: H01L23/00 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L23/532

CPC classification number: H01L24/05 ,  H01L21/31051 ,  H01L21/76807 ,  H01L21/76877 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53295 ,  H01L24/02 ,  H01L24/03 ,  H01L24/48 ,  H01L24/85 ,  H01L24/94 ,  H01L2224/02166 ,  H01L2224/023 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05546 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48247 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate having circuit component and a dielectric layer over the substrate. The dielectric layer includes a plurality of inter level dielectric (ILD) layers and the uppermost dielectric layer includes at least one interconnect. A pad dielectric layer is provided over the uppermost ILD layer. A pad interconnect for receiving a wire bond is formed in the pad dielectric layer. The pad interconnect is coupled to the at least one interconnect of the uppermost ILD layer. A top surface of the pad dielectric layer is substantially coplanar with a top surface of the pad interconnect. A passivation layer is formed over the pad dielectric layer.

Abstract translation: 提出了用于形成装置的装置和方法。 该方法包括在衬底上提供具有电路部件和电介质层的衬底。 电介质层包括多个层间介电层（ILD）层，最上面的介电层包括至少一个互连。 衬垫介电层设置在最上面的ILD层之上。 在焊盘介电层中形成用于接收引线接合的焊盘互连。 焊盘互连耦合到最上面的ILD层的至少一个互连。 焊盘介电层的顶表面与焊盘互连的顶表面基本共面。 在焊盘介电层上形成钝化层。

公开(公告)号：US09437547B2

公开(公告)日：2016-09-06

申请号：US15063526

申请日：2016-03-08

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Benfu Lin ,  Hong Yu ,  Lup San Leong ,  Alex See ,  Wei Lu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/535 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/535 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface.

公开(公告)号：US20160136781A1

公开(公告)日：2016-05-19

申请号：US15005029

申请日：2016-01-25

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Benfu Lin ,  Wei Lu ,  Alex See

IPC: B24B49/00

CPC classification number: B24B49/00 ,  B24B37/005 ,  B24B37/32

Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table; a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes the retaining ring; a sensor for sensing the step height between the retaining ring and its membrane and a controller for adjusting the movement of the retaining ring based on the step height between the retaining ring and its membrane to ensure the step height remains at a fixed value as the retaining ring wears out.

公开(公告)号：US09287197B2

公开(公告)日：2016-03-15

申请号：US13831898

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Benfu Lin ,  Hong Yu ,  Lup San Leong ,  Alex See ,  Wei Lu

IPC: H01L21/44 ,  H01L21/00 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface.

Abstract translation: 公开了一种用于形成装置的装置和方法。 提供衬底，并且通过衬底的顶表面在衬底中形成TSV。 衬底的TSV和顶表面衬有具有第一绝缘层，抛光停止层和第二绝缘层的绝缘堆叠。 在基板上形成导电层。 TSV填充有导电层的导电材料。 将衬底平坦化以除去导电层的过量导电材料。 平坦化停止在抛光停止层上以形成平坦的顶表面。