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    CMP HEAD STRUCTURE
    2.
    发明申请
    CMP HEAD STRUCTURE 有权
    CMP头结构

    公开(公告)号：US20150111469A1

    公开(公告)日：2015-04-23

    申请号：US14059448

    申请日：2013-10-22

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Benfu LIN ,  Lei WANG ,  Xuesong RAO ,  Wei LU ,  Alex SEE

    IPC: B24B37/005 ,  B24B49/16

    CPC classification number: B24B37/005 ,  B24B37/32 ,  B24B49/16

    Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table, a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes a retaining ring, a sensor for sensing the depth of grooves on the retaining ring and a controller for determining an update pressure to apply to the retaining ring based on the depth of the grooves and applying the updated pressure to the retaining ring during processing.

    Abstract translation: 提出了一种用于CMP处理的CMP结构和使用其的装置的制造方法。 该装置包括在压板台上的抛光垫，用于将晶片保持在抛光垫上的头组件，其中头部组件包括保持环，用于感测保持环上的凹槽的深度的传感器，以及用于确定 基于槽的深度更新施加到保持环的压力，并且在处理期间将更新的压力施加到保持环。

    DEVICE ALIGNMENT MARK USING A PLANARIZATION PROCESS
    3.
    发明申请
    DEVICE ALIGNMENT MARK USING A PLANARIZATION PROCESS 审中-公开

    公开(公告)号：US20180233661A1

    公开(公告)日：2018-08-16

    申请号：US15432933

    申请日：2017-02-15

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Benfu LIN ,  Kah Wee GAN ,  Chim Seng SEET

    IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L27/22

    CPC classification number: H01L23/544 ,  H01L27/228 ,  H01L2223/54426 ,  H01L2223/54453

    Abstract: Device and methods of forming a device are disclosed. The method includes providing a substrate and forming a dielectric layer over the substrate. An alignment mark opening which extends through the dielectric layer is formed. A conductive layer is deposited over the dielectric layer. A planarization process is performed to remove excess conductive material on the dielectric layer and recess a top surface of the conductive material in the alignment mark opening with respect to the dielectric layer, forming an alignment mark of the device. A first electrode layer may be formed over the dielectric layer, wherein a topography of the dielectric layer and the alignment mark in the dielectric layer is transferred to the first electrode layer.

    THROUGH SILICON VIAS
    4.
    发明申请
    THROUGH SILICON VIAS 有权
    通过硅胶

    公开(公告)号：US20140264911A1

    公开(公告)日：2014-09-18

    申请号：US13831898

    申请日：2013-03-15

    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.

    Inventor： Benfu LIN ,  Hong Yu ,  Lup San ,  Alex See ,  Wei Lu

    IPC: H01L23/48 ,  H01L21/768

    CPC classification number: H01L23/535 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface.

    Abstract translation: 公开了一种用于形成装置的装置和方法。 提供衬底，并且通过衬底的顶表面在衬底中形成TSV。 衬底的TSV和顶表面衬有具有第一绝缘层，抛光停止层和第二绝缘层的绝缘堆叠。 在基板上形成导电层。 TSV填充有导电层的导电材料。 将衬底平坦化以除去导电层的过量导电材料。 平坦化停止在抛光停止层上以形成平坦的顶表面。

    SEMICONDUCTOR DEVICES AND METHODS OF FORMING SEMICONDUCTOR DEVICES
    5.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF FORMING SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220077234A1

    公开(公告)日：2022-03-10

    申请号：US17016416

    申请日：2020-09-10

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Benfu LIN ,  Yi JIANG ,  Lup San LEONG ,  Juan Boon TAN

    IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

    Abstract: A semiconductor device may be provided, including a first insulating layer; a second insulating layer arranged over the first insulating layer; a memory structure arranged within a memory region and including a resistance changing memory element within the first insulating layer; and a logic structure arranged within a logic region. In the memory region, the first insulating layer may contact the second insulating layer and in the logic region, the semiconductor device may further include a stop layer arranged between the first insulating layer and the second insulating layer.

    CMP HEAD STRUCTURE
    6.
    发明申请
    CMP HEAD STRUCTURE 有权
    CMP头结构

    公开(公告)号：US20150111467A1

    公开(公告)日：2015-04-23

    申请号：US14059451

    申请日：2013-10-22

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Benfu LIN ,  Wei LU ,  Alex SEE

    IPC: B24B49/00

    CPC classification number: B24B49/00 ,  B24B37/005 ,  B24B37/32

    Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table; a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes the retaining ring; a sensor for sensing the step height between the retaining ring and its membrane and a controller for adjusting the movement of the retaining ring based on the step height between the retaining ring and its membrane to ensure the step height remains at a fixed value as the retaining ring wears out.

    Abstract translation: 提出了一种用于CMP处理的CMP结构和使用其的装置的制造方法。 该装置包括在台板上的抛光垫; 用于将晶片保持在抛光垫上的头组件，其中所述头组件包括所述保持环; 用于感测保持环和其膜之间的台阶高度的传感器以及用于基于保持环与其膜之间的台阶高度来调整保持环的移动的控制器，以确保台阶高度保持在固定值作为保持 戒指磨损了。

    THROUGH SILICON VIAS
    8.
    发明申请
    THROUGH SILICON VIAS 有权
    通过硅胶

    公开(公告)号：US20160190066A1

    公开(公告)日：2016-06-30

    申请号：US15063526

    申请日：2016-03-08

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Benfu LIN ,  Hong YU ,  Lup San LEONG ,  Alex SEE ,  Wei LU

    IPC: H01L23/535 ,  H01L23/532 ,  H01L23/528

    CPC classification number: H01L23/535 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface.

    Abstract translation: 公开了一种用于形成装置的装置和方法。 提供衬底，并且通过衬底的顶表面在衬底中形成TSV。 衬底的TSV和顶表面衬有具有第一绝缘层，抛光停止层和第二绝缘层的绝缘堆叠。 在基板上形成导电层。 TSV填充有导电层的导电材料。 将衬底平坦化以除去导电层的过量导电材料。 平坦化停止在抛光停止层上以形成平坦的顶表面。

    CMP HEAD STRUCTURE
    9.
    发明申请
    CMP HEAD STRUCTURE 有权

    公开(公告)号：US20160136774A1

    公开(公告)日：2016-05-19

    申请号：US15005034

    申请日：2016-01-25

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Benfu LIN ,  Lei WANG ,  Xuesong RAO ,  Wei LU ,  Alex SEE

    IPC: B24B37/005

    CPC classification number: B24B37/005 ,  B24B37/32 ,  B24B49/16

    Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table, a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes a retaining ring, a sensor for sensing the depth of grooves on the retaining ring and a controller for determining an update pressure to apply to the retaining ring based on the depth of the grooves and applying the updated pressure to the retaining ring during processing.

    PROGRAMMABLE INTERPOSER USING RRAM PLATFORM
    10.
    发明公开
    PROGRAMMABLE INTERPOSER USING RRAM PLATFORM 审中-公开

    公开(公告)号：US20230301214A1

    公开(公告)日：2023-09-21

    申请号：US17697974

    申请日：2022-03-18

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Lup San LEONG ,  Juan Boon TAN ,  Benfu LIN ,  Yi JIANG

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1233 ,  H01L27/24 ,  H01L45/146 ,  H01L45/1608

    Abstract: According to various embodiments, there may be provided an interposer. The interposer including: a substrate; a dielectric layer disposed on the substrate; a via disposed entirely within the dielectric layer; a resistive film layer disposed to line the via; a metal interconnect disposed in the resistive layer lined via; and a plurality of metal lines disposed in the dielectric layer, the plurality of metal lines including a first metal line connected to the metal interconnect, a second metal line connected to the resistive film layer at a first point, and a third metal line connected to the resistive film layer at a second point.

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