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    Superconducting bump bonds
    11.
    发明授权
    Superconducting bump bonds 有权

    公开(公告)号：US10468579B2

    公开(公告)日：2019-11-05

    申请号：US16062064

    申请日：2015-12-30

    Applicant: Google LLC

    Inventor： Joshua Yousouf Mutus ,  Erik Anthony Lucero

    IPC: H01L23/498 ,  H01L39/04 ,  H01L23/00 ,  H01L25/065 ,  H01L27/18 ,  H01L25/00 ,  H01L25/18

    Abstract: A device (100) includes a first chip (104) having a first circuit element (112), a first interconnect pad (116) in electrical contact (118) with the first circuit element, and a barrier layer (120) on the first interconnect pad, a superconducting bump bond (106) on the barrier layer, and a second chip (102) joined to the first chip by the superconducting bump bond, the second chip having a quantum circuit element (108), in which the superconducting bump bond provides an electrical connection between the first circuit element and the quantum circuit element.

    SIGNAL DISTRIBUTION FOR A QUANTUM COMPUTING SYSTEM
    14.
    发明公开
    SIGNAL DISTRIBUTION FOR A QUANTUM COMPUTING SYSTEM 审中-公开

    公开(公告)号：US20240162050A1

    公开(公告)日：2024-05-16

    申请号：US18516711

    申请日：2023-11-21

    Applicant: Google LLC

    Inventor： Evan Jeffrey ,  Joshua Yousouf Mutus

    IPC: H01L21/48 ,  G06N10/00 ,  H01L23/498 ,  H01L33/06

    CPC classification number: H01L21/4857 ,  G06N10/00 ,  H01L23/49822 ,  H01L33/06

    Abstract: A method of fabricating a carrier chip for distributing signals among circuit elements of a quantum computing device, includes: providing a multilayer wiring stack, the multilayer wiring stack comprising alternating layers of dielectric material and wiring; bonding a capping layer to the multilayer wiring stack, in which the capping layer includes a single crystal silicon dielectric layer; forming a via hole within the capping layer, in which the via hole extends to a first wiring layer of the multilayer wiring stack; forming an electrically conductive via within the via hole and electrically coupled to the first wiring layer; and forming a circuit element on a surface of the capping layer, in which the circuit element is directly electrically coupled to the electrically conductive via.

    INTEGRATED CIRCUIT DESIGN SYSTEM AND METHOD
    15.
    发明公开
    INTEGRATED CIRCUIT DESIGN SYSTEM AND METHOD 审中-公开

    公开(公告)号：US20240126970A1

    公开(公告)日：2024-04-18

    申请号：US18341495

    申请日：2023-06-26

    Applicant: Google LLC

    Inventor： Evan Jeffrey ,  Julian Shaw Kelly ,  Joshua Yousouf Mutus

    IPC: G06F30/39

    CPC classification number: G06F30/39 ,  G06F2111/02

    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for parameterization of physical dimensions of discrete circuit components for component definitions that define discrete circuit components. The component definitions may be selected for use in a device design. When a parametrization of a particular version of a discrete circuit component definition is changed, the version level of the device design is also changed and the circuit layout for the device design is physically verified for the new version level.

    Signal distribution for a quantum computing system
    16.
    发明授权
    Signal distribution for a quantum computing system 有权

    公开(公告)号：US11854833B2

    公开(公告)日：2023-12-26

    申请号：US17263619

    申请日：2018-07-30

    Applicant: Google LLC

    Inventor： Evan Jeffrey ,  Joshua Yousouf Mutus

    IPC: H01L21/48 ,  G06N10/00 ,  H01L23/498 ,  H01L33/06

    CPC classification number: H01L21/4857 ,  G06N10/00 ,  H01L23/49822 ,  H01L33/06

    Abstract: A method of fabricating a carrier chip for distributing signals among circuit elements of a quantum computing device, includes: providing a multilayer wiring stack, the multilayer wiring stack comprising alternating layers of dielectric material and wiring; bonding a capping layer to the multilayer wiring stack, in which the capping layer includes a single crystal silicon dielectric layer; forming a via hole within the capping layer, in which the via hole extends to a first wiring layer of the multilayer wiring stack; forming an electrically conductive via within the via hole and electrically coupled to the first wiring layer; and forming a circuit element on a surface of the capping layer, in which the circuit element is directly electrically coupled to the electrically conductive via.

    INTEGRATING CIRCUIT ELEMENTS IN A STACKED QUANTUM COMPUTING DEVICE
    17.
    发明申请
    INTEGRATING CIRCUIT ELEMENTS IN A STACKED QUANTUM COMPUTING DEVICE 有权

    公开(公告)号：US20230004848A1

    公开(公告)日：2023-01-05

    申请号：US17902731

    申请日：2022-09-02

    Applicant: Google LLC

    Inventor： Julian Shaw Kelly ,  Joshua Yousouf Mutus

    IPC: G06N10/00 ,  H01L25/065 ,  H01L39/14

    Abstract: A stacked quantum computing device including a first chip that includes a first dielectric substrate and a superconducting qubit on the first dielectric substrate, and a second chip that is bonded to the first chip and includes a second dielectric substrate, a qubit readout element on the second dielectric substrate, a control wire on the second dielectric substrate, a dielectric layer covering the control wire, and a shielding layer covering the dielectric layer.

    SUPERCONDUCTING BUMP BONDS
    18.
    发明申请
    SUPERCONDUCTING BUMP BONDS 审中-公开

    公开(公告)号：US20200006620A1

    公开(公告)日：2020-01-02

    申请号：US16557378

    申请日：2019-08-30

    Applicant: Google LLC

    Inventor： Joshua Yousouf Mutus ,  Erik Anthony Lucero

    IPC: H01L39/04 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

    Abstract: A device includes a first chip having a first circuit element, a first interconnect pad in electrical contact with the first circuit element, and a barrier layer on the first interconnect pad, a superconducting bump bond on the barrier layer, and a second chip joined to the first chip by the superconducting bump bond, the second chip having a first quantum circuit element, in which the superconducting bump bond provides an electrical connection between the first circuit element and the first quantum circuit element.

    Integrating circuit elements in a stacked quantum computing device
    19.
    发明授权
    Integrating circuit elements in a stacked quantum computing device 有权

    公开(公告)号：US12217129B2

    公开(公告)日：2025-02-04

    申请号：US17902695

    申请日：2022-09-02

    Applicant: Google LLC

    Inventor： Julian Shaw Kelly ,  Joshua Yousouf Mutus

    IPC: G06N10/00 ,  H01L25/065 ,  H10N60/20

    Abstract: A stacked quantum computing device including a first chip that includes a first dielectric substrate and a superconducting qubit on the first dielectric substrate, and a second chip that is bonded to the first chip and includes a second dielectric substrate, a qubit readout element on the second dielectric substrate, a control wire on the second dielectric substrate, a dielectric layer covering the control wire, and a shielding layer covering the dielectric layer.

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