公开(公告)号：US20050006663A1

公开(公告)日：2005-01-13

申请号：US10614840

申请日：2003-07-08

申请人： Gregory Howard ,  Leland Swanson

发明人： Gregory Howard ,  Leland Swanson

IPC分类号： H01L21/337 ,  H01L29/10 ,  H01L29/808 ,  H01L29/74

CPC分类号： H01L29/66909 ,  H01L29/1058 ,  H01L29/8083

摘要： We disclose the structure of an electronic device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has, near the top surface, a buried layer that is electrically communicable to a drain terminal. The device has a body region over the buried layer. A portion of the body region contacts a gate region connected to a gate terminal. The device has a channel region, of which the length spans the distance between the buried layer and a source region, which projects upward from the channel region and is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.

摘要翻译： 我们公开了电子设备的结构，制造设备的方法和设备的操作。 该器件靠近基板顶部。 在顶表面附近具有可电连接到漏极端子的掩埋层。 该器件在掩埋层上方具有体区。 身体区域的一部分接触连接到栅极端子的栅极区域。 该器件具有沟道区，其长度跨越掩埋层与源极区之间的距离，该距离从沟道区向上突出并连接到源极。 器件电流在通道中基本上垂直于衬底的顶表面流动。

公开(公告)号：US20070281408A1

公开(公告)日：2007-12-06

申请号：US11839832

申请日：2007-08-16

申请人： Gregory Howard ,  Leland Swanson

发明人： Gregory Howard ,  Leland Swanson

IPC分类号： H01L21/337

CPC分类号： H01L29/808 ,  H01L29/0692

摘要： The present invention provides a system for providing a cross-lateral junction field effect transistor (114) having desired high-performance desired voltage, frequency or current characteristics. The cross-lateral transistor is formed on a commercial semiconductor substrate (102). A channel structure (124) is formed along the substrate, having source (120) and drain (122) structures laterally formed on opposites sides thereof. A first gate structure (116) is formed along the substrate, laterally adjoining the channel structure orthogonal to the source and drain structures. A second gate structure (118) is formed along the substrate, laterally adjoining the channel structure, orthogonal to the source and drain structures and opposite the first gate stricture.

摘要翻译： 本发明提供了一种用于提供具有期望的高性能期望电压，频率或电流特性的横向结型场效应晶体管（114）的系统。 横向晶体管形成在商用半导体衬底（102）上。 沿着衬底形成通道结构（124），其具有在其相对侧上横向形成的源极（120）和漏极（122）结构。 第一栅极结构（116）沿着衬底形成，横向邻接与源极和漏极结构正交的沟道结构。 沿着衬底形成第二栅极结构（118），其横向邻接沟道结构，垂直于源极和漏极结构并与第一栅极狭窄相对。

公开(公告)号：US06949454B2

公开(公告)日：2005-09-27

申请号：US10681400

申请日：2003-10-08

申请人： Leland Swanson ,  Gregory Howard

发明人： Leland Swanson ,  Gregory Howard

IPC分类号： H01L21/765 ,  H01L27/08 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/872 ,  H01L21/28 ,  H01L21/44

CPC分类号： H01L29/402 ,  H01L21/765 ,  H01L27/0814 ,  H01L29/417 ,  H01L29/872

摘要： A Schottky device having a substrate layer of a first conductivity type having a surface, and a guard ring formed over the surface of the substrate layer and also surrounding a barrier region of the substrate layer. The guard ring has a gate of a second conductivity type disposed over a dielectric layer. A metal can be formed over the barrier region to form a Schottky junction.

摘要翻译： 具有具有表面的第一导电类型的衬底层的肖特基器件和形成在衬底层的表面上并且还围绕衬底层的阻挡区域的保护环。 保护环具有布置在电介质层上的第二导电类型的栅极。 可以在阻挡区域上形成金属以形成肖特基结。

公开(公告)号：US20050170598A1

公开(公告)日：2005-08-04

申请号：US10767390

申请日：2004-01-29

申请人： Gregory Howard ,  Leland Swanson

发明人： Gregory Howard ,  Leland Swanson

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01G4/008 ,  H01L21/20

CPC分类号： H01L28/75

摘要： A silicided amorphous polysilicon-metal capacitor is formed using a standard process except that the exposed surface of the polycrystalline silicon is transformed into amorphous polysilicon before the silicidation of the polysilicon layer to form the bottom plate of the capacitive element. Transforming the polycrystalline silicon to amorphous polysilicon at the surface renders the top surface of the polysilicon substantially smooth compared to that of the polycrystalline silicon. This in turn renders the surface of the silicide layer, which forms the bottom plate of the capacitor and is formed by the silicidation of the polysilicon, to be substantially smooth as well. Thus, the likelihood of stress points being formed in the dielectric layer of the capacitor is substantially reduced, increasing yield and reliability and permitting a reduction in the thickness which leads to a greater value of capacitance per unit area. The polycrystalline silicon can be rendered amorphous through implantation of a neutral species prior to the silicidation of the polysilicon to form the silicide layer that is used for the bottom plate of the capacitive element.

摘要翻译： 使用标准工艺形成硅化非晶多晶硅 - 金属电容器，不同之处在于，多晶硅层的硅化之前将多晶硅的暴露表面转化为非晶多晶硅，以形成电容元件的底板。 在多晶硅的表面使多晶硅转化为非晶态多晶硅使得多晶硅的顶表面与多晶硅相比基本上平滑。 这又使得形成电容器的底板的硅化物层的表面也通过多晶硅的硅化形成，使其基本平滑。 因此，在电容器的电介质层中形成应力点的可能性大大降低，提高了产量和可靠性，并允许减小厚度，这导致每单位面积的电容值更大。 多晶硅可以在多晶硅硅化之前通过中性物质的注入而变得非晶化，以形成用于电容元件底板的硅化物层。

公开(公告)号：US20050093151A1

公开(公告)日：2005-05-05

申请号：US10696017

申请日：2003-10-29

申请人： Leland Swanson ,  Gregory Howard

发明人： Leland Swanson ,  Gregory Howard

IPC分类号： H01L23/31 ,  H01L23/485 ,  H01L23/498 ,  H01L23/48

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L23/49816 ,  H01L24/13 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/1703 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor circuit comprising a semiconductor die and a package substrate. In one embodiment, a first plurality of conductive bumps serves as a portion of a conductive path between contacts on the semiconductor die and contacts on the package substrate. A second plurality of conductive bumps serves as a portion of a conductive path between other contacts on the die and contacts on the package substrate. Each of the bumps in the first plurality of conductive bumps is larger than each of the bumps in the second plurality of conductive bumps. In another embodiment, the average size of the first plurality of conductive bumps may be at least 20% larger (or greater) than the average size of the second plurality of bumps.

摘要翻译： 一种包括半导体管芯和封装衬底的半导体电路。 在一个实施例中，第一多个导电凸块用作半导体管芯上的触头和封装衬底上的触点之间的导电路径的一部分。 第二组多个导电凸起用作芯片上的其它触头和封装衬底上的触点之间的导电路径的一部分。 第一多个导电凸块中的每个凸起大于第二多个导电凸块中的每个凸点。 在另一个实施例中，第一多个导电凸块的平均尺寸可以比第二多个凸块的平均尺寸大至少20％（或更大）。

公开(公告)号：US20050012111A1

公开(公告)日：2005-01-20

申请号：US10623230

申请日：2003-07-18

申请人： Gregory Howard ,  Leland Swanson

发明人： Gregory Howard ,  Leland Swanson

IPC分类号： H01L21/337 ,  H01L29/808 ,  H01L29/74

CPC分类号： H01L29/66909 ,  H01L29/8083

摘要： We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a body region above the buried layer. A portion of the body region contacts a gate region connected to a gate terminal. The device has a channel region, of which the length spans the distance between the buried layer and a source region, which projects upward from the channel region and is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.

摘要翻译： 我们公开了JFET器件的结构，制造器件的方法和器件的操作。 该器件靠近基板顶部。 它具有可电连接到漏极端子的掩埋层。 它在埋层之上有一个体区。 身体区域的一部分接触连接到栅极端子的栅极区域。 该器件具有沟道区，其长度跨越掩埋层与源极区之间的距离，该距离从沟道区向上突出并连接到源极。 器件电流在通道中基本上垂直于衬底的顶表面流动。

公开(公告)号：US09131364B2

公开(公告)日：2015-09-08

申请号：US14079486

申请日：2013-11-13

申请人： Gregory Howard ,  Susan Chory ,  Tony He

发明人： Gregory Howard ,  Susan Chory ,  Tony He

IPC分类号： H04W4/12 ,  H04W8/22 ,  H04M1/725 ,  H04W4/00 ,  H04W8/18

CPC分类号： H04M1/72563 ,  H04L41/22 ,  H04L61/1594 ,  H04L63/0853 ,  H04M1/72519 ,  H04W4/02 ,  H04W4/12 ,  H04W4/16 ,  H04W4/50 ,  H04W4/60 ,  H04W8/18 ,  H04W8/183 ,  H04W8/22 ,  H04W88/06

摘要： Various user interfaces and other technologies for interacting with devices that support multiple SIM cards can be implemented. For example, intelligent handling of SIM card selection can help users deal with multiple SIM card scenarios. A user interface for overriding SIM card selection can be supported. Users can interact with their devices more efficiently and with less frustration. A wide variety of use default SIM card scenarios are supported. SIM cards can be selected based on any of a rich set of input factors.

摘要翻译： 可以实现用于与支持多个SIM卡的设备进行交互的各种用户界面和其他技术。 例如，智能处理SIM卡选择可以帮助用户处理多个SIM卡方案。 可以支持用于覆盖SIM卡选择的用户界面。 用户可以更有效地与他们的设备进行交互，而且不用担心。 支持各种使用默认SIM卡方案。 可以基于丰富的输入因子中的任何一个来选择SIM卡。

公开(公告)号：US20060209677A1

公开(公告)日：2006-09-21

申请号：US11084600

申请日：2005-03-18

申请人： Michael McGee ,  Mark Enstone ,  Gregory Howard

发明人： Michael McGee ,  Mark Enstone ,  Gregory Howard

IPC分类号： H04L1/00

CPC分类号： H04L41/0609 ,  H04L12/44

摘要： Systems and methods for implementing priority failover determination are disclosed. An exemplary method includes prioritizing ranking criteria for a plurality of network adapter ports based at least in part on user input. The method also includes determining a ranking value for each of the plurality of network adapter ports based on the prioritized ranking criteria. The method further includes designating a primary network adapter port and at least a secondary network adapter port based on the ranking value for each of the plurality of network adapter ports

摘要翻译： 公开了实现优先故障转移确定的系统和方法。 一种示例性方法包括至少部分地基于用户输入来对多个网络适配器端口的排序标准进行优先级排序。 该方法还包括基于优先级排序标准确定多个网络适配器端口中的每一个的排序值。 该方法还包括基于多个网络适配器端口中的每一个的排序值来指定主网络适配器端口和至少第二网络适配器端口

公开(公告)号：US20060197158A1

公开(公告)日：2006-09-07

申请号：US11380602

申请日：2006-04-27

申请人： Jeffrey Babcock ,  Angelo Pinto ,  Scott Balster ,  Alfred Haeusler ,  Gregory Howard

发明人： Jeffrey Babcock ,  Angelo Pinto ,  Scott Balster ,  Alfred Haeusler ,  Gregory Howard

IPC分类号： H01L27/12

CPC分类号： H01L29/66659 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/78612 ,  H01L29/78654

摘要： The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).

摘要翻译： 本发明是一种用于在MOS晶体管结构中形成超陡掺杂分布的方法。 该方法包括在栅极电介质（50）下面形成含碳层（110），并在MOS晶体管的源极和漏极区域（80）形成。 含碳层（110）将防止掺杂剂扩散到栅极电介质层（50）正下方的区域（40）中。

公开(公告)号：US20060099792A1

公开(公告)日：2006-05-11

申请号：US10984150

申请日：2004-11-09

申请人： Gregory Howard ,  Naveen Yanduru

发明人： Gregory Howard ,  Naveen Yanduru

IPC分类号： H01L21/44

CPC分类号： H01L24/85 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01066 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： Disclosed are wirebonding methods wherein bondwires are positioned using dynamically determined variations in die placement. Preferred methods of the invention include steps for placing a die on the prepared substrate using selected ideal placement coordinates. Deviation of the actual die placement from the selected ideal placement coordinates is monitored, and one ore more critical bondwires are wirebonded between respective die pins and pins-on the substrate. The monitored placement deviation is used to dynamically position the critical bondwires on the critical pins according to actual die placement. Disclosed embodiments include methods using lateral deviation monitoring and angular deviation monitoring to dynamically position bondwires.

摘要翻译： 公开了引线键合方法，其中使用动态确定的管芯放置的变化来定位焊丝。 本发明的优选方法包括使用选择的理想放置坐标将管芯放置在所制备的衬底上的步骤。 监测实际管芯位置与所选择的理想放置坐标的偏差，并且一个或多个关键焊接线在相应的管芯引脚和引脚之间引线接合在衬底上。 监控的放置偏差用于根据实际的管芯位置动态地将关键焊接线定位在关键销上。 公开的实施例包括使用横向偏差监测和角度偏差监测来动态地定位键合线的方法。