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    CROSSPOINT ARRAY DECODER
    11.
    发明申请
    CROSSPOINT ARRAY DECODER 审中-公开

    公开(公告)号：US20170287540A1

    公开(公告)日：2017-10-05

    申请号：US15507790

    申请日：2014-09-25

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Brent Buchanan ,  Amit S. Sharma ,  Gary Gibson ,  Erik Ordentlich ,  Naveen Muralimanohar

    IPC: G11C8/10 ,  G11C13/00

    CPC classification number: G11C8/10 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028

    Abstract: Example implementations disclosed herein can be used to decode memory elements in a crosspoint array. In one example implementation, a drain voltage is applied to a drain terminal of a field effect transistor switch for a selected row in the crosspoint array associated with the selected memory element. A bulk terminal of the field effect transistor switch for the selected row can be biased with a well voltage that is independent of the drain, source, or substrate voltages. In such examples, the gate terminal of the field effect transistor switch for the selected row can be driven with a gate voltage comprising the drain voltage and the well voltage. The drain voltage, the well voltage, and the gate voltage are selected to cause the field effect transistor switch for the selected row to operate as an ohmic switch.

    DATA STORING IN MEMORY ARRAYS
    13.
    发明申请
    DATA STORING IN MEMORY ARRAYS 有权
    数据存储在存储器阵列中

    公开(公告)号：US20160350000A1

    公开(公告)日：2016-12-01

    申请号：US15113890

    申请日：2014-01-31

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Erik Ordentlich ,  Ron M. Roth

    IPC: G06F3/06 ,  G11C29/52 ,  G06F11/10

    CPC classification number: G06F3/064 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/0238 ,  G06F12/0607 ,  G11C29/52 ,  G11C2029/0411

    Abstract: Methods and systems for storing data in memory arrays are described. In one implementation, input bits are encoded into an intermediate binary array having multiple sub-arrays iteratively appended row-wise to the intermediate binary array. First sub-array is generated based on the input bits such that each row of the first sub-array has a number of 1's equal to a fraction of number of columns in the first sub-array, and based on a column balance coding such that the columns of the first sub-array have an equal number of 1's. At least one subsequent sub-array is generated based on a set of bits obtained from balancing termination indices for a previous sub-array and from diagonal bits of the intermediate binary array that are a part of the previous appended sub-array. The intermediate binary array is transformed to an encoded bit pattern. The encoded bit pattern is stored in the memory array.

    Abstract translation: 描述了将数据存储在存储器阵列中的方法和系统。 在一个实现中，输入比特被编码成具有逐行地附加到中间二进制数组的多个子阵列的中间二进制数组。 基于输入比特生成第一子阵列，使得第一子阵列的每行的数目等于第一子阵列中的列数量的一部分，并且基于列平衡编码，使得 第一个子阵列的列具有相等数量的1。 基于从先前子阵列的平衡终止索引和作为前一个附加子阵列的一部分的中间二进制数组的对角位获得的一组比特来生成至少一个后续子阵列。 将中间二进制数组变换为编码位模式。 编码位模式存储在存储器阵列中。

    MEMRISTOR MEMORY
    15.
    发明申请
    MEMRISTOR MEMORY 审中-公开
    仪表存储器

    公开(公告)号：US20160351259A1

    公开(公告)日：2016-12-01

    申请号：US15111981

    申请日：2014-01-24

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Yoocharn Jeon ,  Erik Ordentlich ,  Gregg B. Lesartre ,  Siamak Tavallaei

    IPC: G11C13/00 ,  G06F11/10 ,  G11C29/52 ,  G11C29/12

    CPC classification number: G11C13/0069 ,  G06F11/1048 ,  G06F11/1068 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0064 ,  G11C29/12 ,  G11C29/52 ,  G11C2013/0076

    Abstract: A memristor memory is disclosed. In an example, the memristor memory comprises a memristor component having a plurality of memristor cells. Each memristor cell is configured to change state based on application of an electric potential. The memristor memory also comprises a controller to read the state of the plurality of memristor cells and identify a subset of the plurality of memristor cells to rewrite. The controller writes the subset of the plurality of memristor cells, and the controller reads an updated state of the plurality of memristor cells to validate the subset was written correctly.

    Abstract translation: 忆阻记忆体被公开。 在一个示例中，忆阻器存储器包括具有多个忆阻单元的忆阻器部件。 每个忆阻器单元被配置为基于施加电位而改变状态。 忆阻器存储器还包括控制器，用于读取多个忆阻单元的状态，并且识别多个忆阻器单元的子集以重写。 控制器写入多个忆阻器单元的子集，并且控制器读取多个忆阻器单元的更新状态以验证该子集被正确写入。

    DATA STORING IN MEMORY ARRAYS
    16.
    发明申请
    DATA STORING IN MEMORY ARRAYS 审中-公开
    数据存储在存储器阵列中

    公开(公告)号：US20160329097A1

    公开(公告)日：2016-11-10

    申请号：US15111703

    申请日：2014-01-30

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Erik Ordentlich ,  Ron M. Roth

    IPC: G11C13/00 ,  G06F3/06

    CPC classification number: G06F17/30 ,  G06F3/0604 ,  G06F3/0638 ,  G06F3/0679 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069

    Abstract: Methods and systems for storing data in memory arrays are described. In one implementation, a data storage system includes a memory array having memory devices in a crossbar configuration, and a memory controller for controlling data storage in the memory array. The memory controller includes an encoder to generate a 2-dimensional encoded bit pattern that encodes the input data. Each run-length of 0's and each run-length of 1's in each row or each column of the encoded bit pattern are at least of a predefined lower limit. The predefined lower limit is at least two. The memory controller includes a write controller to write the encoded bit pattern into the memory devices of the memory array, such that a number of consecutive memory devices in each row or each column of the memory array having a same state is based on the encoded bit pattern.

    Abstract translation: 描述了将数据存储在存储器阵列中的方法和系统。 在一个实现中，数据存储系统包括具有交叉开关配置的存储器件的存储器阵列和用于控制存储器阵列中的数据存储的存储器控​​制器。 存储器控制器包括编码器，用于产生对输入数据进行编码的2维编码位模式。 编码比特模式的每行或每列的每个游程长度为0，每个游程长度为1，至少为预定义的下限。 预定义的下限至少为2。 存储器控制器包括写控制器，用于将编码位模式写入存储器阵列的存储器件，使得存储器阵列的每行或每列中具有相同状态的多个连续存储器件基于编码位 模式。

    Storing run-length limited two-dimensional encoded bit patterns in memory arrays
    17.
    发明授权
    Storing run-length limited two-dimensional encoded bit patterns in memory arrays 有权

    公开(公告)号：US10102205B2

    公开(公告)日：2018-10-16

    申请号：US15111703

    申请日：2014-01-30

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Erik Ordentlich ,  Ron M. Roth

    IPC: G06F17/30 ,  G11C13/00 ,  G06F3/06

    Abstract: In one implementation, a data storage system includes a memory array having memory devices in a crossbar configuration, and a memory controller for controlling data storage in the memory array. The memory controller includes an encoder to generate a 2-dimensional encoded bit pattern that encodes an input data. Each run-length of 0's and each run-length of 1's in each row or each column of the encoded bit pattern are at least of a predefined lower limit. The predefined lower limit is at least two. The memory controller includes a write controller to write the encoded bit pattern into the memory devices of the memory array, such that a number of consecutive memory devices in each row or each column of the memory array having a same state is based on the encoded bit pattern.

    Reusing sneak current in accessing memory cells
    18.
    发明授权
    Reusing sneak current in accessing memory cells 有权

    公开(公告)号：US10049733B2

    公开(公告)日：2018-08-14

    申请号：US15500062

    申请日：2014-10-31

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Naveen Muralimanohar ,  Erik Ordentlich ,  Yoocharn Jeon

    IPC: G11C13/00

    Abstract: A method to access two memory cells include determining a first cell current flowing through a first memory cell by subtracting a sneak current associated with the first memory cell from a first access current of the first bitline and determining a second cell current flowing through a second memory cell in the first bitline or a second bitline by subtracting the sneak current associated with the first memory cell from a second access current of the first bitline or the second bitline.

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