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    PROGRAMMING MEMORY CONTROLLERS TO ALLOW PERFORMANCE OF ACTIVE MEMORY OPERATIONS
    12.
    发明申请
    PROGRAMMING MEMORY CONTROLLERS TO ALLOW PERFORMANCE OF ACTIVE MEMORY OPERATIONS 审中-公开
    编程存储器控制器允许有效存储器操作的性能

    公开(公告)号：US20160239211A1

    公开(公告)日：2016-08-18

    申请号：US15025616

    申请日：2013-09-30

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Kevin T. Lim ,  Naveen Muralimanohar

    IPC: G06F3/06

    CPC classification number: G06F3/0605 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/1689

    Abstract: Example implementations relate to performing active memory operations. In example implementations, a memory controller may be programmed such that the memory controller allocates more time for a standard memory operation than required by a timing specification of a memory communicatively coupled to the memory controller. Extra time that is allocated for the standard memory operation may be identified. An active memory operation may be performed during the extra time.

    Abstract translation: 示例实现涉及执行主动存储器操作。 在示例实现中，可以对存储器控制器进行编程，使得存储器控制器为通信地耦合到存储器控制器的存储器的定时指定所需的标准存储器操作分配更多的时间。 可以识别分配给标准存​​储器操作的额外时间。 可以在额外时间期间执行活动存储器操作。

    Processing in-memory architectures for performing logical operations
    13.
    发明授权
    Processing in-memory architectures for performing logical operations 有权

    公开(公告)号：US11126549B2

    公开(公告)日：2021-09-21

    申请号：US16073202

    申请日：2016-03-31

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Naveen Muralimanohar ,  Ali Shafiee Ardestani

    IPC: G06F7/57 ,  G06F12/0802 ,  G06F15/78 ,  G06N3/063 ,  G06N3/04 ,  G06F17/16 ,  G06N3/08

    Abstract: In an example, a method includes identifying, using at least one processor, data portions of a plurality of distinct data objects stored in at least one memory which are to be processed using the same logical operation. The method may further include identifying a representation of an operand stored in at least one memory, the operand being to provide the logical operation and providing a logical engine with the operand. The data portions may be stored in a plurality of input data buffers, wherein each of the input data buffers comprises a data portion of a different data object. The logical operation may be carried out on each of the data portions using the logical engine, and the outputs for each data portion may be stored in a plurality of output data buffers, wherein each of the outputs comprising data derived from a different data object.

    Data processing using resistive memory arrays
    14.
    发明授权
    Data processing using resistive memory arrays 有权

    公开(公告)号：US10942673B2

    公开(公告)日：2021-03-09

    申请号：US15571340

    申请日：2016-03-31

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Ali Shafiee Ardestani ,  Naveen Muralimanohar

    IPC: G06F3/06 ,  G11C7/10 ,  G11C13/00 ,  G06F13/16 ,  G06N3/063

    Abstract: In an example, a method includes receiving, in a memory, input data to be processed in a first and a second processing layer. A processing operation of the second layer may be carried out on an output of a processing operation of the first processing layer. The method may further include assigning the input data to be processed according to at least one processing operation of the first layer, which may comprise using a resistive memory array, and buffering output data. It may be determined whether the buffered output data exceeds a threshold data amount to carry out at least one processing operation of the second layer and when it is determined that the buffered output data exceeds the threshold data amount, at least a portion of the buffered output data may be assigned to be processed according to a processing operation of the second layer.

    In situ transposition
    15.
    发明授权
    In situ transposition 有权

    公开(公告)号：US10698975B2

    公开(公告)日：2020-06-30

    申请号：US16063793

    申请日：2016-01-27

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Naveen Muralimanohar ,  Benjamin Feinberg ,  John Paul Strachan

    IPC: G06F17/16 ,  G11C13/00 ,  G06G7/16 ,  G11C7/16

    Abstract: Example implementations of the present disclosure relate to in situ transposition of the data values in a memory array. An example system may include a non-volatile memory (NVM) array, including a plurality of NVM elements, usable in performance of computations. The example system may include an input engine to input a plurality of data values for storage by a corresponding plurality of original NVM elements. The example system may further include a transposition engine to direct performance of the in situ transposition such that the plurality of data values remains stored by the original NVM elements.

    FLOATING POINT DATA SET COMPRESSION
    16.
    发明申请
    FLOATING POINT DATA SET COMPRESSION 审中-公开

    公开(公告)号：US20200091930A1

    公开(公告)日：2020-03-19

    申请号：US16131722

    申请日：2018-09-14

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Anirban Nag ,  Naveen Muralimanohar ,  Paolo Faraboschi

    IPC: H03M7/30 ,  H03M7/24

    Abstract: Computer-implemented methods, systems, and devices to perform lossless compression of floating point format time-series data are disclosed. A first data value may be obtained in floating point format representative of an initial time-series parameter. For example, an output checkpoint of a computer simulation of a real-world event such as weather prediction or nuclear reaction simulation. A first predicted value may be determined representing the parameter at a first checkpoint time. A second data value may be obtained from the simulation. A prediction error may be calculated. Another predicted value may be generated for a next point in time and may be adjusted by the previously determined prediction error (e.g., to increase accuracy of the subsequent prediction). When a third data value is obtained, the adjusted prediction value may be used to generate a difference (e.g., XOR) for storing in a compressed data store to represent the third data value.

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