公开(公告)号：US20200150872A1

公开(公告)日：2020-05-14

申请号：US16744795

申请日：2020-01-16

Applicant: Huawei Technologies Co., Ltd.

Inventor： Zehan Cui ,  Mingyu Chen ,  Yao Liu ,  Yuan Ruan

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F12/06

Abstract: In a method for accessing an extended memory, after receiving a first memory access request from a processor system in a computer, an extended memory controller sends a read request for obtaining to-be-accessed data to the extended memory and return, to the processor system, a first response message indicating the to-be-accessed data has not been obtained. The extended memory controller writes the to-be-accessed data into a data buffer after receiving the to-be-accessed data returned by the extended memory. After receiving, from the processor system, a second memory access request comprising a second access address, the extended memory controller returns, to the processor system, the to-be-accessed data in the data buffer in response to the second memory access request, wherein the second access address is different from the first access address and points to the physical address of the to-be-accessed data.

公开(公告)号：US20170075818A1

公开(公告)日：2017-03-16

申请号：US15343693

申请日：2016-11-04

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Yao Liu ,  Yongbing Huang ,  Mingyu Chen ,  Zehan Cui ,  Licheng Chen ,  Yuan Ruan

IPC: G06F12/1027 ,  G06F12/1009 ,  G06F3/06

CPC classification number: G06F12/1027 ,  G06F3/0608 ,  G06F3/0619 ,  G06F3/0647 ,  G06F3/0652 ,  G06F3/0664 ,  G06F3/0685 ,  G06F12/1009 ,  G06F2212/1024 ,  G06F2212/684

Abstract: A memory management method and a device, where the method includes: receiving a memory access request, where the memory access request carries a virtual address; determining a page fault type of the virtual address if finding, in a translation lookaside buffer TLB and a memory, no page table entry corresponding to the virtual address; allocating a corresponding page to the virtual address if the page fault type of the virtual address is a blank-page-caused page fault, where the blank-page-caused page fault means that no corresponding page is allocated to the virtual address; and updating the page table entry corresponding to the virtual address to the memory and the TLB. The memory manager does not generate a page fault when a blank-page-caused page fault occurs, but allocates a corresponding page to the virtual address. Therefore, a quantity of occurrences of the page fault is reduced, thereby improving memory management efficiency.

Abstract translation: 一种存储器管理方法和装置，其中所述方法包括：接收存储器访问请求，其中所述存储器访问请求携带虚拟地址; 如果在翻译后备缓冲器TLB和存储器中找到与虚拟地址相对应的页表条目，则确定虚拟地址的页面错误类型; 如果虚拟地址的页面错误类型是由空白页引起的页面错误，其中由空白页引起的页面错误意味着没有对应的页面被分配给虚拟地址，则将对应的页面分配给虚拟地址; 以及将与虚拟地址相对应的页表条目更新到存储器和TLB。 当出现空白页引起的页面错误时，内存管理器不会生成页面错误，但会将相应的页面分配给虚拟地址。 因此，页面错误的发生量减少，从而提高存储器管理效率。

公开(公告)号：US20150293859A1

公开(公告)日：2015-10-15

申请号：US14751368

申请日：2015-06-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yongbing Huang ,  Mingyu Chen ,  Yuan Ruan ,  Licheng Chen

IPC: G06F12/14 ,  G06F3/06

CPC classification number: G06F12/1458 ,  G06F3/0622 ,  G06F3/0635 ,  G06F3/0683 ,  G06F13/1642 ,  G06F2212/1016 ,  G06F2212/1052 ,  G11C7/1003 ,  G11C7/1075

Abstract: A memory access processing method is based on memory chip interconnection, a memory chip, and a system, which relate to the field of electronic devices, and can shorten a time delay in processing a memory access request and improve a utilization rate of system bandwidth. The method of the present invention includes: receiving, by a first memory chip, a memory access request; and if the first memory chip is not a target memory chip corresponding to the memory access request, sending, according to a preconfigured routing rule, the memory access request to a next memory chip connected with the first memory chip, until the target memory chip corresponding to the memory access request is determined. Embodiments of the present invention are mainly used in a process of processing a memory access request.

Abstract translation: 存储器访问处理方法基于与电子设备领域相关的存储器芯片互连，存储器芯片和系统，并且可以缩短处理存储器访问请求的时间延迟并提高系统带宽的利用率。 本发明的方法包括：由第一存储器芯片接收存储器访问请求; 并且如果第一存储器芯片不是与存储器访问请求对应的目标存储器芯片，则根据预配置的路由规则将存储器访问请求发送到与第一存储器芯片连接的下一个存储器芯片，直到目标存储器芯片对应 到存储器访问请求被确定。 本发明的实施例主要用于处理存储器访问请求的过程。

公开(公告)号：US20150006841A1

公开(公告)日：2015-01-01

申请号：US14335029

申请日：2014-07-18

Applicant: Huawei Technologies Co., Ltd.

Inventor： Mingyu Chen ,  Yuan Ruan ,  Zehan Cui ,  Licheng Chen ,  Yongbing Huang ,  Mingyang Chen

IPC: G06F13/16

CPC classification number: G06F13/1673 ,  G06F13/4239

Abstract: A message-based memory access apparatus and an access method thereof are disclosed, The message-based memory access apparatus includes: a message-based command bus, configured to transmit a message-based memory access instruction generated by the CPU to instruct a memory system to perform a corresponding operation; a message-based memory controller, configured to package a CPU request into a message packet and sent the packet to a storage module, and parse a message packet returned by the storage module and return data to the CPU; a message channel, configured to transmit a request message packet and a response message packet; and the storage module, including a buffer scheduler, and configured to receive the request packet from the message-based memory controller and process the corresponding request.

Abstract translation: 公开了一种基于消息的存储器访问装置及其访问方法，基于消息的存储器访问装置包括：基于消息的命令总线，被配置为发送由CPU生成的基于消息的存储器访问指令，以指示存储器系统 执行相应的操作; 基于消息的存储器控​​制器，被配置为将CPU请求打包到消息分组中并将所述分组发送到存储模块，并且解析由所述存储模块返回的消息分组并将数据返回到所述CPU; 消息信道，被配置为发送请求消息分组和响应消息分组; 以及所述存储模块，包括缓冲器调度器，并且被配置为从所述基于消息的存储器控​​制器接收所述请求分组并处理相应的请求。

公开(公告)号：US10976956B2

公开(公告)日：2021-04-13

申请号：US16366325

申请日：2019-03-27

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Tianyue Lu ,  Mingyu Chen ,  Yuan Ruan ,  Wei Yang

IPC: G06F3/06 ,  G06F12/0873 ,  G06F16/903 ,  G06F13/14 ,  H04L12/801

Abstract: In a non-volatile memory (NVM) persistence method, a memory controller maintains a plurality of memory write instruction sets that are locked separately for persistence of write operations. A credit value for monitoring a quantity of completed write instructions is configured for each of the plurality of memory write instruction sets, and a credit value is also configured for each of a plurality of medium write instruction sets maintained by a medium controller and corresponding respectively to the memory write instruction sets. After a memory write instruction set is locked in response to a persistence query, the credit value of a corresponding medium write instruction set is used as means for the memory controller to determine whether the write instructions in the locked memory write instruction set have been completed by the medium controller.

公开(公告)号：US20190220224A1

公开(公告)日：2019-07-18

申请号：US16366325

申请日：2019-03-27

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Tianyue Lu ,  Mingyu Chen ,  Yuan Ruan ,  Wei Yang

IPC: G06F3/06 ,  G06F16/903

CPC classification number: G06F3/0656 ,  G06F3/0619 ,  G06F3/0679 ,  G06F12/0873 ,  G06F16/903

Abstract: In a non-volatile memory (NVM) persistence method, a memory controller maintains a plurality of memory write instruction sets that are locked separately for persistence of write operations. A credit value for monitoring a quantity of completed write instructions is configured for each of the plurality of memory write instruction sets, and a credit value is also configured for each of a plurality of medium write instruction sets maintained by a medium controller and corresponding respectively to the memory write instruction sets. After a memory write instruction set is locked in response to a persistence query, the credit value of a corresponding medium write instruction set is used as means for the memory controller to determine whether the write instructions in the locked memory write instruction set have been completed by the medium controller.

公开(公告)号：US20190196989A1

公开(公告)日：2019-06-27

申请号：US16289134

申请日：2019-02-28

Applicant: Huawei Technologies Co., Ltd.

Inventor： Tianyue Lu ,  Yuan Ruan ,  Mingyu Chen ,  Shaojie Chen

IPC: G06F13/16 ,  G06F13/18 ,  G06F13/372 ,  G06F3/06 ,  G06F9/30

CPC classification number: G06F13/1673 ,  G06F3/06 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0679 ,  G06F9/30101 ,  G06F13/1642 ,  G06F13/1668 ,  G06F13/18 ,  G06F13/372 ,  G11C7/1051 ,  G11C7/1063

Abstract: A storage system includes a memory controller and a memory device, and the memory device includes a medium controller, a memory, and a buffer. The medium controller is configured to write, into the buffer after receiving an access request, data requested by the access request. The memory controller is configured to send a query request to the medium controller after sending the access request to the medium controller, where the query request is used to query whether data has been written into the buffer. The medium controller is further configured to determine, based on the query request, whether data has been written into the buffer, and send the data that has been written into the buffer to the memory controller when there is data in the buffer.

公开(公告)号：US09898421B2

公开(公告)日：2018-02-20

申请号：US14751368

申请日：2015-06-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yongbing Huang ,  Mingyu Chen ,  Yuan Ruan ,  Licheng Chen

IPC: G06F12/02 ,  G06F12/14 ,  G06F3/06 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F12/1458 ,  G06F3/0622 ,  G06F3/0635 ,  G06F3/0683 ,  G06F13/1642 ,  G06F2212/1016 ,  G06F2212/1052 ,  G11C7/1003 ,  G11C7/1075

Abstract: A memory access processing method is based on memory chip interconnection, a memory chip, and a system, which relate to the field of electronic devices, and can shorten a time delay in processing a memory access request and improve a utilization rate of system bandwidth. The method of the present disclosure includes receiving, by a first memory chip, a memory access request; and if the first memory chip is not a target memory chip corresponding to the memory access request, sending, according to a preconfigured routing rule, the memory access request to a next memory chip connected with the first memory chip, until the target memory chip corresponding to the memory access request is determined. Embodiments of the present disclosure are mainly used in a process of processing a memory access request.

公开(公告)号：US20150220135A1

公开(公告)日：2015-08-06

申请号：US14685272

申请日：2015-04-13

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Yongbing Huang ,  Mingyu Chen ,  Yuan Ruan

IPC: G06F1/32

CPC classification number: G06F1/3225 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/0647 ,  G06F3/068 ,  G06F9/5016 ,  G06F9/5094 ,  G06F12/0638 ,  G06F2212/1028 ,  G06F2212/205 ,  G06F2212/251 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/154 ,  Y02D10/22 ,  Y02D50/20

Abstract: A method for reducing power consumption of a memory system and a memory controller are provided. The method for reducing power consumption of a memory system includes: determining whether a dynamic random access memory DRAM memory module with a low access frequency exists in a memory system; when a DRAM memory module with a low access frequency exists, transfer, according to a size of a working set in the memory system, page data that does not belong to the working set to a non-volatile memory NVM memory module, where the page data that does not belong to the working set is page data that does not need to be accessed when a process runs within preset time.

Abstract translation: 提供了一种用于降低存储器系统和存储器控制器的功耗的方法。 用于降低存储器系统的功耗的方法包括：确定存储系统中是否存在具有低存取频率的动态随机存取存储器DRAM存储器模块; 当存在具有低访问频率的DRAM存储器模块时，根据存储器系统中的工作集的大小将不属于工作集的页面数据传送到非易失性存储器NVM存储器模块，其中页面 不属于工作集的数据是当一个进程在预设时间内运行时不需要访问的页面数据。