利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

63 条记录 (耗时 0.053 秒)

    Non-volatile semiconductor memory with NAND cell structure and switching transistors with different channel lengths to reduce punch-through
    14.
    发明授权
    Non-volatile semiconductor memory with NAND cell structure and switching transistors with different channel lengths to reduce punch-through 失效
    具有NAND单元结构的非易失性半导体存储器和具有不同通道长度的开关晶体管以减少穿通

    公开(公告)号：US5508957A

    公开(公告)日：1996-04-16

    申请号：US312072

    申请日：1994-09-26

    申请人： Masaki Momodomi ,  Fujio Masuoka ,  Yasuo Itoh ,  Hiroshi Iwahashi ,  Yoshihisa Iwata ,  Masahiko Chiba ,  Satoshi Inoue ,  Riichiro Shirota ,  Ryozo Nakayama ,  Kazunori Ohuchi ,  Shigeyoshi Watanabe ,  Ryouhei Kirisawa

    发明人： Masaki Momodomi ,  Fujio Masuoka ,  Yasuo Itoh ,  Hiroshi Iwahashi ,  Yoshihisa Iwata ,  Masahiko Chiba ,  Satoshi Inoue ,  Riichiro Shirota ,  Ryozo Nakayama ,  Kazunori Ohuchi ,  Shigeyoshi Watanabe ,  Ryouhei Kirisawa

    IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30 ,  H01L27/115 ,  G11C16/06 ,  H01L29/788

    CPC分类号： G11C16/30 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  H01L27/115

    摘要： An erasable programmable read-only memory with NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and a series array of memory cell transistors, and a switching transistor connected between the series array of memory cell transistors and ground. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data writing mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive, so that this cell block is connected to the corresponding bit line. Under such a condition, a decoder circuit stores a desired data (a logic "one" e.g.) in the selected cell, by applying an "H" level voltage to the bit line, applying an "L" level voltage to a word line connected to the selected cell, applying the "H" level voltage to a memory cell or cells positioned between the selected cell and the bit line, and applying the "L" level voltage to a memory cell or cells positioned between the selected cell and the ground. The selection transistor and switching transistor for a corresponding series array of memory cell transistors have different channel lengths to reduce punch through.

    摘要翻译： 具有NAND单元结构的可擦除可编程只读存储器包括NAND单元块，每个单元块具有连接到对应位线的选择晶体管和存储单元晶体管的串联阵列，以及连接在串联阵列存储单元之间的开关晶体管 晶体管和地。 每个单元晶体管具有浮置栅极和控制栅极。 字线连接到单元晶体管的控制栅极。 在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通，使得该单元块连接到对应的位线。 在这种情况下，解码器电路通过向位线施加“H”电平电压，将所需数据（例如逻辑“1”）存储在所选择的单元中，对连接的字线施加“L”电平电压 将“H”电平施加到位于所选择的单元和位线之间的存储单元或单元，并将“L”电平施加到位于所选单元和地之间的存储单元或单元 。 用于存储单元晶体管的相应串联阵列的选择晶体管和开关晶体管具有不同的沟道长度以减少穿通。

    Electrically erasable programmable read-only memory with threshold value controller for data programming and method of programming the same
    16.
    发明授权
    Electrically erasable programmable read-only memory with threshold value controller for data programming and method of programming the same 失效
    电可擦除可编程只读存储器，具有用于数据编程的阈值控制器和编程方法

    公开(公告)号：US5831903A

    公开(公告)日：1998-11-03

    申请号：US868138

    申请日：1997-06-03

    申请人： Kazunori Ohuchi ,  Tomoharu Tanaka ,  Yoshihisa Iwata ,  Yasuo Itoh ,  Masaki Momodomi ,  Fujio Masuoka

    发明人： Kazunori Ohuchi ,  Tomoharu Tanaka ,  Yoshihisa Iwata ,  Yasuo Itoh ,  Masaki Momodomi ,  Fujio Masuoka

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C29/00 ,  G11C29/12 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/06

    CPC分类号： G11C16/3459 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3454

    摘要： A NAND cell type electrically erasable programmable read-only memory has a memory array section containing NAND cell units. Each NAND cell unit has a series array of floating gate type metal-oxide semiconductor field effect transistors as memory cell transistors. The memory section is associated with a control-gate controller, a data-latch circuit, a sense amplifier section, and a data comparator, which is connected via an output buffer to a verify-termination detector. When a data is once written into a selected memory cell in a data programming mode, a specific basing voltage is applied to the selected cell so that the actual electrical data write condition of the selected memory cell is verified. If the comparator detects that the verified write condition is dissatisfied, data-rewriting operations are repeatedly executed by additionally supplied the selected cell with a suitable voltage which compensates for the dissatisfaction of the verified write condition in the selected memory cell transistor.

    摘要翻译： NAND单元型电可擦除可编程只读存储器具有包含NAND单元单元的存储器阵列部分。 每个NAND单元单元具有作为存储单元晶体管的浮栅型金属氧化物半导体场效应晶体管的串联阵列。 存储器部分与控制门控制器，数据锁存电路，读出放大器部分和数据比较器相关联，其经由输出缓冲器连接到验证终止检测器。 当在数据编程模式中将数据一次写入所选择的存储单元中时，将特定的基准电压施加到所选择的单元，以便验证所选存储单元的实际电数据写入条件。 如果比较器检测到验证的写入条件不满意，则通过用选择的存储单元晶体管补偿所验证的写入条件的不满足的适当电压来额外提供所选择的单元来重复执行数据重写操作。

    Sense amplifier for use in an EEPROM
    17.
    发明授权
    Sense amplifier for use in an EEPROM 失效
    用于EEPROM的感应放大器

    公开(公告)号：US5740112A

    公开(公告)日：1998-04-14

    申请号：US583533

    申请日：1996-01-04

    申请人： Tomoharu Tanaka ,  Yoshiyuki Tanaka ,  Kazunori Ohuchi ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Koji Sakui ,  Shinji Saito ,  Hideki Sumihara

    发明人： Tomoharu Tanaka ,  Yoshiyuki Tanaka ,  Kazunori Ohuchi ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Koji Sakui ,  Shinji Saito ,  Hideki Sumihara

    IPC分类号： G11C7/06 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C7/00

    CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3454 ,  G11C7/067

    摘要： A sense amplifier for signal detection for use in an electrically erasable and programmable read-only memory (EEPROM). The sense amplifier includes a first clock signal-synchronized inverter including a first inverter and first switch for switching between activating and deactivating states of the first inverter, the first clock signal-synchronized inverter having a first input connected to a corresponding one of the bit lines and a first output. A second clock signal-synchronized inverter is arranged in parallel with the first clock signal-synchronized inverter and includes a second inverter and a second switch for switching between activating and deactivating states of the second inverter, the second clock signal-synchronized inverter having an input connected to the output of the first clock signal-synchronized inverter and an output connected to the input of the first clock signal-synchronized inverter. The switches in the first and second clock signal-synchronized inverters are activated with a delay so that a potential on the corresponding bit line is reliably sensed and latched at the output of the first clock signal-synchronized inverter.

    摘要翻译： 用于电可擦除和可编程只读存储器（EEPROM）中的信号检测用读出放大器。 读出放大器包括：第一时钟信号同步反相器，包括第一反相器和用于在第一反相器的激活和去激活状态之间切换的第一开关，第一时钟信号同步反相器具有连接到对应的一个位线的第一输入 和第一个输出。 第二时钟信号同步反相器与第一时钟信号同步反相器并联布置，并且包括第二反相器和用于在第二反相器的激活和去激活状态之间切换的第二开关，第二时钟信号同步反相器具有输入 连接到第一时钟信号同步反相器的输出端，以及连接到第一时钟信号同步反相器的输入端的输出端。 第一和第二时钟信号同步反相器中的开关被延迟激活，使得对应位线上的电位被可靠地感测并锁存在第一时钟信号同步反相器的输出端。

    Electrically erasable programmable read-only memory with threshold value controller for data programming
    18.
    发明授权
    Electrically erasable programmable read-only memory with threshold value controller for data programming 失效
    电可擦除可编程只读存储器，具有用于数据编程的阈值控制器

    公开(公告)号：US5657270A

    公开(公告)日：1997-08-12

    申请号：US376665

    申请日：1995-01-23

    申请人： Kazunori Ohuchi ,  Tomoharu Tanaka ,  Yoshihisa Iwata ,  Yasuo Itoh ,  Masaki Momodomi ,  Fujio Masuoka

    发明人： Kazunori Ohuchi ,  Tomoharu Tanaka ,  Yoshihisa Iwata ,  Yasuo Itoh ,  Masaki Momodomi ,  Fujio Masuoka

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C29/00 ,  G11C29/12 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/06

    CPC分类号： G11C16/3459 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3454

    摘要： A non-volatile semiconductor memory device including a plurality of bit lines; a plurality of word lines insulatively intersecting the bit lines; a memory cell array including a plurality of memory cells coupled to the bit lines and the word lines, each memory cell including a transistor with a charge storage portion; a plurality of programming circuits coupled to the memory cell array (i) for storing data which define whether or not write voltages are to be applied to respective of the memory cells, (ii) for selectively applying the write voltages to a part of the memory cells, which part is selected according to the data stored in the plurality of programing circuits, (iii) for determining actual written states of the memory cells, and (iv) for selectively modifying the stored data based on a predetermined logical relationship between the determined actual written states of the memory cells and the data stored in the plurality of programming circuits, thereby applying the write voltages only to memory cells which are not sufficiently written to achieve a predetermined written state.

    摘要翻译： 一种包括多个位线的非易失性半导体存储器件; 多个字线与位线绝对相交; 包括耦合到位线和字线的多个存储单元的存储单元阵列，每个存储单元包括具有电荷存储部分的晶体管; 耦合到存储单元阵列（i）的多个编程电路，用于存储定义是否将写入电压施加到存储单元的相应数据的数据，（ii）用于选择性地将写入电压施加到存储器的一部分 单元，根据存储在多个编程电路中的数据选择该部分，（iii）用于确定存储单元的实际写入状态，以及（iv）基于所确定的预定逻辑关系来选择性地修改所存储的数据 存储单元的实际写入状态和存储在多个编程电路中的数据，从而将写入电压仅施加到未被充分写入以实现预定写入状态的存储单元。

    Semiconductor integrated circuits
    19.
    发明授权
    Semiconductor integrated circuits 失效
    半导体集成电路

    公开(公告)号：US4751676A

    公开(公告)日：1988-06-14

    申请号：US911799

    申请日：1986-09-26

    申请人： Masaki Momodomi

    发明人： Masaki Momodomi

    IPC分类号： H01L27/10 ,  G11C7/14 ,  G11C11/408 ,  H01L21/8242 ,  H01L27/108 ,  G11C13/00

    CPC分类号： G11C7/14 ,  G11C11/4082

    摘要： A semiconductor integrated circuit, comprises a semiconductor integrated circuit chip; a standard voltage generating means for generating standard voltage other than a supply voltage and a ground voltage, at least one, standard voltage wire for supplying the standard voltage to at least one circuit of said semiconductor integrated circuit chip; at least one first capacitor extending along the standard voltage wire, the first capacitor having the standard voltage wire as one electrode thereof, and the other electrode connected to the supply voltage; and at least one second capacitor extending along the standard voltage wire, the second capacitor having the standard voltage wire as one electrode thereof, and the other electrode connected to the ground voltage.

    摘要翻译： 一种半导体集成电路，包括半导体集成电路芯片; 用于产生除电源电压和接地电压以外的标准电压的标准电压产生装置，至少一个用于向所述半导体集成电路芯片的至少一个电路提供标准电压的标准电压线; 至少一个沿标准电压线延伸的第一电容器，第一电容器具有作为其一个电极的标准电压线，而另一个电极连接到电源电压; 以及沿着标准电压线延伸的至少一个第二电容器，所述第二电容器具有作为其一个电极的标准电压线，而另一个电极连接到接地电压。