公开(公告)号：US08030182B2

公开(公告)日：2011-10-04

申请号：US11992230

申请日：2005-09-20

申请人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Hiroshi Akahori

发明人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Hiroshi Akahori

IPC分类号： H01L21/461 ,  B08B7/04

CPC分类号： H01L21/306 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/66795 ,  H01L29/785

摘要： By hydrogen-terminating a semiconductor surface using a solution containing HF2− ions and an oxidant, the hydrogen termination can be quickly carried out. In this case, the semiconductor surface is silicon having a (111) surface, a (110) surface, or a (551) surface.

摘要翻译： 通过使用含有HF 2 - 离子和氧化剂的溶液氢终止半导体表面，可以快速进行氢终止。 在这种情况下，半导体表面是具有（111）表面，（110）表面或（551）表面的硅。

公开(公告)号：US20110062460A1

公开(公告)日：2011-03-17

申请号：US12948913

申请日：2010-11-18

申请人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Akihiro Morimoto

发明人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Akihiro Morimoto

IPC分类号： H01L51/52

CPC分类号： H05B33/28 ,  H01L51/5206 ,  H01L51/5253 ,  H01L51/529 ,  H01L2251/5361 ,  H05B33/04

摘要： An organic EL light emitting element is provided with a conductive transparent electrode 3, a counter electrode 8 opposing the conductive transparent electrode 3, an organic EL light emitting layer 6 provided between the conductive transparent electrode 3 and the counter electrode 8, an insulating protection layer 9 provided to cover at least the organic EL light emitting layer 6, and a heat dissipating layer 11 which is brought into contact with the insulating protection layer 9. The conductive transparent electrode has an ITO film including at least one of Hf, V and Zr at least on the surface part on the side of the organic EL light emitting layer 6, and the insulating protection layer 9 includes a nitride film having a thickness of 100 nm or less.

摘要翻译： 有机EL发光元件设置有导电透明电极3，与导电透明电极3相对的对置电极8，设置在导电性透明电极3和对置电极8之间的有机EL发光层6，绝缘保护层 设置为至少覆盖有机EL发光层6，以及与绝缘保护层9接触的散热层11.导电性透明电极具有含有Hf，V，Zr中的至少一种的ITO膜 至少在有机EL发光层6侧的表面部分上，绝缘保护层9包括厚度为100nm以下的氮化物膜。

公开(公告)号：US07902595B2

公开(公告)日：2011-03-08

申请号：US12308057

申请日：2007-05-31

申请人： Alberto O. Adan ,  Mitsuhiro Kikuta ,  Akinobu Teramoto ,  Tadahiro Ohmi ,  Hiroo Yabe ,  Takanori Watanabe

发明人： Alberto O. Adan ,  Mitsuhiro Kikuta ,  Akinobu Teramoto ,  Tadahiro Ohmi ,  Hiroo Yabe ,  Takanori Watanabe

IPC分类号： H01L29/66 ,  H01L21/8239

CPC分类号： H01L29/7813 ,  H01L21/823412 ,  H01L21/823456 ,  H01L21/823487 ,  H01L21/823807 ,  H01L21/82385 ,  H01L21/823885 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/045 ,  H01L29/4236 ,  H01L29/66734

摘要： In one embodiment of the present invention, a power IC device is disclosed containing a power MOS transistor with a low ON resistance and a surface channel MOS transistor with a high operation speed. There is also provided a method of manufacturing such a device. A chip has a surface of which the planar direction is not less than −8° and not more than +8° off a silicon crystal face. The p-channel trench power MOS transistor includes a trench formed vertically from the surface of the chip, a gate region in the trench, an inversion channel region on a side wall of the trench, a source region in a surface layer of the chip, and a drain region in a back surface layer of the chip. The surface channel MOS transistor has an inversion channel region fabricated so that an inversion channel current flows in a direction not less than −8° and not more than +8° off the silicon crystal direction.

摘要翻译： 在本发明的一个实施例中，公开了一种功率IC器件，其包含具有低导通电阻的功率MOS晶体管和具有高操作速度的表面沟道MOS晶体管。 还提供了制造这种装置的方法。 芯片的表面的平面方向不小于硅晶面的-8°且不大于+ 8°。 p沟道沟槽功率MOS晶体管包括从芯片的表面垂直形成的沟槽，沟槽中的栅极区域，沟槽的侧壁上的反转沟道区域，芯片的表面层中的源极区域， 以及芯片的背面层中的漏极区域。 表面沟道MOS晶体管具有制造的反向沟道区域，使得反向沟道电流在与硅晶体方向不同于-8°且不超过+ 8°的方向上流动。

公开(公告)号：US20100216300A1

公开(公告)日：2010-08-26

申请号：US12675289

申请日：2008-08-07

申请人： Hirokazu Ueda ,  Toshihisa Nozawa ,  Takaaki Matsuoka ,  Akinobu Teramoto ,  Tadahiro Ohmi

发明人： Hirokazu Ueda ,  Toshihisa Nozawa ,  Takaaki Matsuoka ,  Akinobu Teramoto ,  Tadahiro Ohmi

IPC分类号： H01L21/28

CPC分类号： H01L21/02164 ,  C23C16/511 ,  H01J37/32192 ,  H01L21/02274 ,  H01L21/31055 ,  H01L21/31116

摘要： A semiconductor device manufacturing method, the method including: forming a semiconductor element on a semiconductor substrate; and by using microwaves as a plasma source, forming an insulation film on the semiconductor element by performing a CVD process using microwave plasma having an electron temperature of plasma lower than 1.5 eV and an electron density of plasma higher than 1×1011 cm−3 near a surface of the semiconductor substrate.

摘要翻译： 一种半导体器件制造方法，所述方法包括：在半导体衬底上形成半导体元件; 并且通过使用微波作为等离子体源，通过使用具有低于1.5eV的等离子体的电子温度和高于1×10 11 cm -3的等离子体的电子密度的微波等离子体进行CVD工艺，在半导体元件上形成绝缘膜 半导体衬底的表面。

公开(公告)号：US20100173477A1

公开(公告)日：2010-07-08

申请号：US11991908

申请日：2005-09-13

申请人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Hiroshi Akahori

发明人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Hiroshi Akahori

IPC分类号： H01L21/30 ,  B05C9/06 ,  B08B7/04 ,  B05C9/12 ,  B05C11/00 ,  B08B3/00

CPC分类号： H01L21/3003 ,  B65G2201/0247 ,  H01L21/31 ,  H01L29/6659 ,  H01L29/7833

摘要： A cause of deteriorating the hydrogen termination on the surface of a wafer is found to be water adsorbed on the surface. By exposing the wafer to an inert gas atmosphere containing an H2 gas so as to suppress the oxidation reaction due to the water, it is possible to improve the hydrogen termination on the wafer surface.

摘要翻译： 发现晶片表面的氢终止劣化的原因是水被吸附在表面上。 通过将晶片暴露于含有H 2气体的惰性气体气氛中以抑制由于水引起的氧化反应，可以改善晶片表面上的氢终止。

公开(公告)号：US20100059830A1

公开(公告)日：2010-03-11

申请号：US12309245

申请日：2007-07-12

申请人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Rihito Kuroda

发明人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Rihito Kuroda

IPC分类号： H01L29/417 ,  H01L27/092

CPC分类号： H01L29/045 ,  H01L21/02057 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/82385 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/518 ,  H01L29/785 ,  H01L2029/7857

摘要： In a semiconductor device, the degree of flatness of 0.3 nm or less in terms of a peak-to-valley (P-V) value is realized by rinsing a silicon surface with hydrogen-added ultrapure water in a light-screened state and in a nitrogen atmosphere and a contact resistance of 10−11 Ωcm2 or less is realized by setting a work function difference of 0.2 eV or less between an electrode and the silicon. Thus, the semiconductor device can operate on a frequency of 10 GHz or higher.

摘要翻译： 在半导体装置中，以峰 - 谷（PV）值为单位，平坦度为0.3nm以下的程度是通过在加有荧光的状态下加氢的超纯水冲洗硅表面而实现的 通过在电极和硅之间设定0.2eV以下的功函数差来实现10-11＆OHgr·cm 2以下的接触电阻。 因此，半导体器件可以在10GHz或更高的频率上工作。

公开(公告)号：US20100025821A1

公开(公告)日：2010-02-04

申请号：US12521019

申请日：2007-12-20

申请人： Tadahiro Ohmi ,  Tetsuya Goto ,  Akinobu Teramoto ,  Takaaki Matsuoka

发明人： Tadahiro Ohmi ,  Tetsuya Goto ,  Akinobu Teramoto ,  Takaaki Matsuoka

IPC分类号： H01L29/30 ,  C23C16/00 ,  H01L21/265

CPC分类号： H01L21/265 ,  H01J37/3222 ,  H01J37/32412 ,  H01J37/32706 ,  H01J2237/20 ,  H01J2237/26 ,  H01L21/26513 ,  H01L21/2658 ,  H01L29/30 ,  H01L29/7833

摘要： When positively charged ions are implanted into a target substrate, charge-up damage may occur on the target substrate. In order to suppress charge-up caused by secondary electrons emitted from the target substrate when positively charged ions are implanted, a conductive member is installed at a position facing the target substrate and electrically grounded with respect to a high frequency. Further, a field intensity generated in the target substrate may be reduced by controlling an RF power applied to the target substrate in pulse mode.

摘要翻译： 当将带正电荷的离子注入目标衬底时，目标衬底上可能会发生充电损伤。 为了抑制当注入正电荷的离子时从目标衬底发射的二次电子引起的充电，导电构件安装在面向目标衬底并相对于高频电接地的位置。 此外，可以通过以脉冲模式控制施加到目标衬底的RF功率来减小在目标衬底中产生的场强。

公开(公告)号：US20090263306A1

公开(公告)日：2009-10-22

申请号：US12425247

申请日：2009-04-16

申请人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Sumio Sano ,  Fusao Fujita

发明人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Sumio Sano ,  Fusao Fujita

IPC分类号： C01B31/36 ,  C23C16/00

CPC分类号： C23C16/325 ,  C23C16/01 ,  C23C16/56 ,  H01L23/49866 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/024 ,  H05K1/0306 ,  H05K3/0011 ,  H05K2203/1105 ,  H01L2924/00

摘要： A silicon carbide substrate has a high-frequency loss equal to or less than 2.0 dB/mm at 20 GHz is effective to mount and operate electronic components. The silicon carbide substrate is heated at 2000° C. or more to be reduced to the high-frequency loss equal to 2.0 dB/mm or less at 20 GHz. Moreover, manufacturing the silicon carbide substrate by CVD without flowing nitrogen into a heater enables the high-frequency loss to be reduced to 2.0 dB/mm or less.

摘要翻译： 在20GHz时，碳化硅衬底具有等于或小于2.0dB / mm的高频损耗有效地安装和操作电子元件。 将碳化硅衬底在2000℃或更高温度下加热至20GHz时降低至2.0dB / mm以下的高频损耗。 此外，通过CVD制造碳化硅衬底，而不将氮气流入加热器，能够将高频损耗降低到2.0dB / mm以下。

公开(公告)号：US07411274B2

公开(公告)日：2008-08-12

申请号：US10543166

申请日：2004-01-29

申请人： Hideki Yamanaka ,  Kiyoshi Demizu ,  Tadahiro Ohmi ,  Akinobu Teramoto ,  Shigetoshi Sugawa

发明人： Hideki Yamanaka ,  Kiyoshi Demizu ,  Tadahiro Ohmi ,  Akinobu Teramoto ,  Shigetoshi Sugawa

IPC分类号： H01L29/04

CPC分类号： H01L21/28167 ,  H01L21/02008 ,  H01L21/02027 ,  H01L21/02381 ,  H01L21/02428 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02658 ,  H01L29/045

摘要： The present invention has been made in order to manufacture a silicon semiconductor substrate used for a semiconductor integrated circuit device, higher in carrier mobility, especially in electron mobility, which is a carrier of an n-type FET, on a {100} plane as a main surface, and provides a silicon semiconductor substrate and a method for manufacturing the same, wherein the conventional RCA cleaning is employed without the use of special cleaning and the surface of the substrate is planarized at an atomic level to thereby decrease the surface roughness thereof without the use of the radical oxidation. The present invention provides a silicon semiconductor substrate comprising: a {110} plane or a plane inclined from a {110} plane as a main surface of the substrate; and steps arranged at an atomic level along a orientation on the main surface.

摘要翻译： 本发明是为了制造用于半导体集成电路器件的硅半导体衬底，在{100}面作为载流子迁移率，尤其是作为n型FET的载流子的电子迁移率中，作为 主表面，并提供硅半导体衬底及其制造方法，其中采用常规的RCA清洗而不使用特殊的清洁，并且基板的表面在原子级平坦化，从而降低其表面粗糙度 而不使用自由基氧化。 本发明提供了一种硅半导体衬底，其包括：{110}面或从{110}面倾斜作为衬底的主表面的平面; 以及沿着主表面沿<110>方向布置在原子水平的台阶。

公开(公告)号：US20080187747A1

公开(公告)日：2008-08-07

申请号：US11883421

申请日：2006-01-20

申请人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Tetsuya Goto ,  Kazumasa Kawase

发明人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Tetsuya Goto ,  Kazumasa Kawase

IPC分类号： H01L21/3205 ,  H01L21/31

CPC分类号： H01L21/02332 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/3185 ,  H01L29/518 ,  Y10T428/265

摘要： A dielectric film wherein N in the state of an Si3=≡N bonding is present in a concentration of 3 atomic % or more in the surface side of an oxide film and also is present in a concentration of 0.1 atomic % or less in the interface side of the oxide film can achieve the prevention of the B diffusion and also the prevention of the deterioration of the NBTI resistance in combination. When the Ar/N2 radical nitridation is used, it is difficult for the resultant oxide film to satisfy the condition wherein N in the above bonding state is present in a concentration of 3 atomic % or more in the surface side of an oxide film and simultaneously is present in a concentration of 0.1 atomic % or less in the interface side of the oxide film, whereas, the above distribution of the N concentration can be achieved by using any of the gas combinations of Xe/N2, Kr/N2, Ar/NH3, Xe/NH3, Kr/NH3, Ar/N2/H2, Xe/N2/H2 and Kr/N2/H2.

摘要翻译： 在氧化物膜的表面侧以3原子％以上的浓度存在Si 3 N 3≡N键的状态下的N的电介质膜，其浓度为 在氧化膜的界面侧为0.1原子％以下，可以防止B扩散，并且可以防止NBTI电阻的组合劣化。 当使用Ar / N 2自由基氮化时，所得到的氧化物膜难以满足在上述接合状态下的N以3原子％以上的浓度存在的条件 氧化膜的表面侧，同时在氧化膜的界面侧以0.1原子％以下的浓度存在，而N浓度的上述分布可以通过使用Xe / N / 2，Kr / N 2，Ar / NH 3，Xe / NH 3，Kr / NH 2， 2/3/2/2/2/2/2/2 和Kr / N 2 H 2 / H 2。