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公开(公告)号:US07902595B2
公开(公告)日:2011-03-08
申请号:US12308057
申请日:2007-05-31
申请人: Alberto O. Adan , Mitsuhiro Kikuta , Akinobu Teramoto , Tadahiro Ohmi , Hiroo Yabe , Takanori Watanabe
发明人: Alberto O. Adan , Mitsuhiro Kikuta , Akinobu Teramoto , Tadahiro Ohmi , Hiroo Yabe , Takanori Watanabe
IPC分类号: H01L29/66 , H01L21/8239
CPC分类号: H01L29/7813 , H01L21/823412 , H01L21/823456 , H01L21/823487 , H01L21/823807 , H01L21/82385 , H01L21/823885 , H01L27/088 , H01L27/0922 , H01L29/045 , H01L29/4236 , H01L29/66734
摘要: In one embodiment of the present invention, a power IC device is disclosed containing a power MOS transistor with a low ON resistance and a surface channel MOS transistor with a high operation speed. There is also provided a method of manufacturing such a device. A chip has a surface of which the planar direction is not less than −8° and not more than +8° off a silicon crystal face. The p-channel trench power MOS transistor includes a trench formed vertically from the surface of the chip, a gate region in the trench, an inversion channel region on a side wall of the trench, a source region in a surface layer of the chip, and a drain region in a back surface layer of the chip. The surface channel MOS transistor has an inversion channel region fabricated so that an inversion channel current flows in a direction not less than −8° and not more than +8° off the silicon crystal direction.
摘要翻译: 在本发明的一个实施例中,公开了一种功率IC器件,其包含具有低导通电阻的功率MOS晶体管和具有高操作速度的表面沟道MOS晶体管。 还提供了制造这种装置的方法。 芯片的表面的平面方向不小于硅晶面的-8°且不大于+ 8°。 p沟道沟槽功率MOS晶体管包括从芯片的表面垂直形成的沟槽,沟槽中的栅极区域,沟槽的侧壁上的反转沟道区域,芯片的表面层中的源极区域, 以及芯片的背面层中的漏极区域。 表面沟道MOS晶体管具有制造的反向沟道区域,使得反向沟道电流在与硅晶体方向不同于-8°且不超过+ 8°的方向上流动。
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公开(公告)号:US20090302382A1
公开(公告)日:2009-12-10
申请号:US12308057
申请日:2007-05-31
申请人: Alberto O. Adan , Mitsuhiro Kikuta , Akinobu Teramoto , Tadahiro Ohmi , Hiroo Yabe , Takanori Watanabe
发明人: Alberto O. Adan , Mitsuhiro Kikuta , Akinobu Teramoto , Tadahiro Ohmi , Hiroo Yabe , Takanori Watanabe
IPC分类号: H01L27/088 , H01L21/8238 , H01L29/78 , H01L21/336 , H01L27/092 , H01L21/8234
CPC分类号: H01L29/7813 , H01L21/823412 , H01L21/823456 , H01L21/823487 , H01L21/823807 , H01L21/82385 , H01L21/823885 , H01L27/088 , H01L27/0922 , H01L29/045 , H01L29/4236 , H01L29/66734
摘要: In one embodiment of the present invention, a power IC device is disclosed containing a power MOS transistor with a low ON resistance and a surface channel MOS transistor with a high operation speed. There is also provided a method of manufacturing such a device. A chip has a surface of which the planar direction is not less than −8° and not more than +8° off a silicon crystal face. The p-channel trench power MOS transistor includes a trench formed vertically from the surface of the chip, a gate region in the trench, an inversion channel region on a side wall of the trench, a source region in a surface layer of the chip, and a drain region in a back surface layer of the chip. The surface channel MOS transistor has an inversion channel region fabricated so that an inversion channel current flows in a direction not less than −8° and not more than +8° off the silicon crystal direction.
摘要翻译: 在本发明的一个实施例中,公开了一种功率IC器件,其包含具有低导通电阻的功率MOS晶体管和具有高操作速度的表面沟道MOS晶体管。 还提供了制造这种装置的方法。 芯片的表面的平面方向不小于硅晶面的-8°且不大于+ 8°。 p沟道沟槽功率MOS晶体管包括从芯片的表面垂直形成的沟槽,沟槽中的栅极区域,沟槽的侧壁上的反转沟道区域,芯片的表面层中的源极区域, 以及芯片的背面层中的漏极区域。 表面沟道MOS晶体管具有制造的反向沟道区域,使得反向沟道电流在与硅晶体方向不同于-8°且不大于+ 8°的方向上流动。
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3.
公开(公告)号:US07928518B2
公开(公告)日:2011-04-19
申请号:US12568415
申请日:2009-09-28
IPC分类号: H01L29/76
CPC分类号: H01L29/7813 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L29/045 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66734
摘要: In a P-channel power MIS field effect transistor formed on a silicon surface having substantially a (110) plane, a gate insulation film is used which provides a gate-to-source breakdown voltage of 10 V or more, and planarizes the silicon surface, or contains Kr, Ar, or Xe.
摘要翻译: 在形成在具有(110)面的硅表面上的P沟道功率MIS场效应晶体管中,使用提供10V以上的栅极 - 源极击穿电压的栅极绝缘膜,并平坦化硅表面 ,或含有Kr,Ar或Xe。
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公开(公告)号:US20100072519A1
公开(公告)日:2010-03-25
申请号:US12568415
申请日:2009-09-28
IPC分类号: H01L29/04
CPC分类号: H01L29/7813 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L29/045 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66734
摘要: In a P-channel power MIS field effect transistor formed on a silicon surface having substantially a (110) plane, a gate insulation film is used which provides a gate-to-source breakdown voltage of 10 V or more, and planarizes the silicon surface, or contains Kr, Ar, or Xe.
摘要翻译: 在形成在具有(110)面的硅表面上的P沟道功率MIS场效应晶体管中,使用提供10V以上的栅极 - 源极击穿电压的栅极绝缘膜,并平坦化硅表面 ,或含有Kr,Ar或Xe。
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5.
公开(公告)号:US07663195B2
公开(公告)日:2010-02-16
申请号:US11285772
申请日:2005-11-22
IPC分类号: H01L29/76
CPC分类号: H01L29/7813 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L29/045 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66734
摘要: In a P-channel power MIS field effect transistor formed on a silicon surface having substantially a (110) plane, a gate insulation film is used which provides a gate-to-source breakdown voltage of 10 V or more, and planarizes the silicon surface, or contains Kr, Ar, or Xe.
摘要翻译: 在形成在具有(110)面的硅表面上的P沟道功率MIS场效应晶体管中,使用提供10V以上的栅极 - 源极击穿电压的栅极绝缘膜,并平坦化硅表面 ,或含有Kr,Ar或Xe。
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6.
公开(公告)号:US20060138538A1
公开(公告)日:2006-06-29
申请号:US11285772
申请日:2005-11-22
IPC分类号: H01L29/76
CPC分类号: H01L29/7813 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L29/045 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66734
摘要: In a P-channel power MIS field effect transistor formed on a silicon surface having substantially a (110) plane, a gate insulation film is used which provides a gate-to-source breakdown voltage of 10 V or more, and planarizes the silicon surface, or contains Kr, Ar, or Xe.
摘要翻译: 在形成在具有(110)面的硅表面上的P沟道功率MIS场效应晶体管中,使用提供10V以上的栅极 - 源极击穿电压的栅极绝缘膜,并平坦化硅表面 ,或含有Kr,Ar或Xe。
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7.
公开(公告)号:US09230799B2
公开(公告)日:2016-01-05
申请号:US13981048
申请日:2012-01-23
申请人: Akinobu Teramoto , Hiroshi Kambayashi , Hirokazu Ueda , Yuichiro Morozumi , Katsushige Harada , Kazuhide Hasebe , Tadahiro Ohmi
发明人: Akinobu Teramoto , Hiroshi Kambayashi , Hirokazu Ueda , Yuichiro Morozumi , Katsushige Harada , Kazuhide Hasebe , Tadahiro Ohmi
IPC分类号: H01L29/20 , H01L21/02 , H01L21/28 , H01L29/66 , H01L29/778 , H01L29/423 , H01L23/00 , H01L29/205 , H01L29/51
CPC分类号: H01L21/02274 , H01L21/02164 , H01L21/02178 , H01L21/022 , H01L21/0228 , H01L21/0254 , H01L21/28264 , H01L23/564 , H01L29/2003 , H01L29/205 , H01L29/42364 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/66462 , H01L29/778 , H01L29/7787 , H01L2924/0002 , H01L2924/00
摘要: A method for fabricating a semiconductor device including GaN (gallium nitride) that composes a semiconductor layer and includes forming a gate insulating film, in which at least one film selected from the group of a SiO2 film and an Al2O3 film is formed on a nitride layer containing GaN by using microwave plasma and the formed film is used as at least a part of the gate insulating film.
摘要翻译: 一种制造半导体器件的方法,该半导体器件包括构成半导体层并包括形成栅极绝缘膜的GaN(氮化镓),其中在氮化物层上形成选自SiO 2膜和Al 2 O 3膜中的至少一种膜 通过使用微波等离子体形成含GaN的GaN,并且将形成的膜用作栅极绝缘膜的至少一部分。
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公开(公告)号:US08492879B2
公开(公告)日:2013-07-23
申请号:US12681576
申请日:2008-10-06
申请人: Tadahiro Ohmi , Akinobu Teramoto , Tomoyuki Suwa , Rihito Kuroda , Hideo Kudo , Yoshinori Hayamizu
发明人: Tadahiro Ohmi , Akinobu Teramoto , Tomoyuki Suwa , Rihito Kuroda , Hideo Kudo , Yoshinori Hayamizu
IPC分类号: H01L29/04
CPC分类号: H01L29/045 , H01L21/02381 , H01L21/02433 , H01L29/78
摘要: On a surface of a semiconductor substrate, a plurality of terraces formed stepwise by an atomic step are formed in the substantially same direction. Using the semiconductor substrate, a MOS transistor is formed so that no step exists in a carrier traveling direction (source-drain direction).
摘要翻译: 在半导体基板的表面上,以大致相同的方向形成有以原子台阶逐步形成的多个台阶。 使用半导体衬底,形成MOS晶体管,使得在载流子行进方向(源 - 漏方向)上不存在台阶。
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公开(公告)号:US08362567B2
公开(公告)日:2013-01-29
申请号:US12309245
申请日:2007-07-12
申请人: Tadahiro Ohmi , Akinobu Teramoto , Rihito Kuroda
发明人: Tadahiro Ohmi , Akinobu Teramoto , Rihito Kuroda
IPC分类号: H01L21/70
CPC分类号: H01L29/045 , H01L21/02057 , H01L21/28194 , H01L21/28202 , H01L21/823807 , H01L21/823835 , H01L21/82385 , H01L21/84 , H01L27/1203 , H01L29/41766 , H01L29/456 , H01L29/518 , H01L29/785 , H01L2029/7857
摘要: In a semiconductor device, the degree of flatness of 0.3 nm or less in terms of a peak-to-valley (P-V) value is realized by rinsing a silicon surface with hydrogen-added ultrapure water in a light-screened state and in a nitrogen atmosphere and a contact resistance of 10−11 Ωcm2 or less is realized by setting a work function difference of 0.2 eV or less between an electrode and the silicon. Thus, the semiconductor device can operate on a frequency of 10 GHz or higher.
摘要翻译: 在半导体装置中,以峰 - 谷(PV)值为单位,平坦度为0.3nm以下的程度是通过在加有荧光的状态下加氢的超纯水冲洗硅表面而实现的 通过在电极和硅之间设定0.2eV以下的功函数差来实现10-11&OHgr·cm 2以下的接触电阻。 因此,半导体器件可以在10GHz或更高的频率上工作。
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公开(公告)号:US20120234491A1
公开(公告)日:2012-09-20
申请号:US13469851
申请日:2012-05-11
申请人: Tadahiro OHMI , Akinobu Teramoto
发明人: Tadahiro OHMI , Akinobu Teramoto
IPC分类号: B05B1/18 , C23C16/511 , C23C16/50
CPC分类号: H01L21/3065 , C23C16/402 , C23C16/511 , H01J37/32192 , H01J37/3244 , H01J37/32449
摘要: A plasma processing apparatus in which consumption of expensive krypton and xenon gases is suppressed as much as possible while reducing damage on a workpiece during plasma processing. In plasma processing of a substrate using a rare gas, two or more kinds of different rare gases are employed, and an inexpensive argon gas is used as one rare gas and any one or both of krypton and xenon gases having a larger collision cross-sectional area against electron than that of the argon gas is used as the other gas. Consequently, consumption of expensive krypton and xenon gases is suppressed as much as possible and damage on a workpiece is reduced during plasma processing.
摘要翻译: 一种等离子体处理装置,其中尽可能地抑制昂贵的氪气和氙气的消耗,同时减少等离子体处理期间对工件的损坏。 在使用稀有气体的基板的等离子体处理中,使用两种以上的不同种类的稀有气体,廉价的氩气用作一种稀有气体,氪气和氙气气体中的任何一种或两者具有较大的碰撞横截面 作为其他气体,使用与氩气相比的电子区域。 因此,尽可能地抑制昂贵的氪气和氙气的消耗,并且在等离子体处理期间减少了工件上的损坏。
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