公开(公告)号：US20150370488A1

公开(公告)日：2015-12-24

申请号：US14764659

申请日：2013-05-22

Applicant: Hitachi, Ltd.

Inventor： Satoru WATANABE ,  Junji OGAWA ,  Nagamasa MIZUSHIMA

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0608 ,  G06F3/06 ,  G06F3/064 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/04 ,  G06F2212/401 ,  G06F2212/7202

Abstract: An example of the invention is a memory device including a controller and a plurality of randomly accessible memories that are capable of storing user data from a host. The controller includes data management information managing correspondence relations between address areas to be designated by the host and the plurality of memories, and compression policy management information managing associations of the address areas to be designated by the host with priorities in compressing user data to be stored in the plurality of memories. The controller is configured to determine a compression policy associated with a designated address area included in an access request from the host based on a priority associated with the designated address area and information on free space of the plurality of memories.

Abstract translation: 本发明的示例是包括控制器和能够存储来自主机的用户数据的多个可随机访问的存储器的存储器件。 控制器包括管理要由主机指定的地址区与多个存储器之间的对应关系的数据管理信息，以及管理要由主机指定的地址区域的关联的压缩策略管理信息，压缩要存储的用户数据的优先级 在多个存储器中。 控制器被配置为基于与指定的地址区域相关联的优先级和关于多个存储器的空闲空间的信息来确定与来自主机的访问请求中包括的指定地址区域相关联的压缩策略。

公开(公告)号：US20150153957A1

公开(公告)日：2015-06-04

申请号：US14615109

申请日：2015-02-05

Applicant: HITACHI, LTD.

Inventor： Tsukasa SHIBAYAMA ,  Akifumi SUZUKI ,  Nobuhiro MAKI ,  Junji OGAWA ,  Masayasu ASANO

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0625 ,  G06F3/0644 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/0246 ,  G06F2212/7207 ,  G11C11/5621 ,  G11C29/82 ,  Y02D10/13

Abstract: A storage system, which comprises multiple memory cells and a storage controller, wherein the storage controller manages cell mode information, which either directly or indirectly denotes the number of bits to be stored in multiple memory cells. The cell mode information can be changed in accordance with a request from a management system.

Abstract translation: 一种存储系统，其包括多个存储器单元和存储控制器，其中所述存储控制器管理单元模式信息，所述单元模式信息直接或间接地表示要存储在多个存储器单元中的位数。 小区模式信息可以根据来自管理系统的请求而改变。

公开(公告)号：US20140321208A1

公开(公告)日：2014-10-30

申请号：US14329171

申请日：2014-07-11

Applicant: HITACHI, LTD.

Inventor： Atsushi KAWAMURA ,  Junji OGAWA

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G06F3/0608 ,  G06F3/0616 ,  G06F3/0641 ,  G06F3/0679 ,  G06F3/0688 ,  G06F11/1044 ,  G06F11/108 ,  G06F12/0246 ,  G06F2212/7202 ,  G11C16/04

Abstract: Data capacity efficiency is improved by de-duplicating data assigned with a code that is different for each data. A storage apparatus comprising a flash memory control device equipped with one or more flash memory modules, wherein the flash memory module comprises at least one flash memory chip for providing a storage area, and a controller for controlling writing/reading of data including user data and a guarantee code accompanying the user data to and from the storage area provided by the flash memory chip, wherein the controller respectively divides a plurality of the data having the common user data into the user data and the guarantee code, stores one of the user data in an area of a predetermined unit of the storage area, and links and stores each of the guarantee codes accompanying the plurality of user data in an area of a predetermined unit of the storage area.

Abstract translation: 通过使用与每个数据不同的代码分配的数据进行解除复制来提高数据容量效率。 一种存储装置，包括配备有一个或多个闪速存储器模块的闪速存储器控制装置，其中所述闪速存储器模块包括用于提供存储区域的至少一个闪速存储器芯片，以及用于控制对包括用户数据的数据的写入/读取的控制器， 伴随着闪存芯片所提供的存储区域的用户数据的保证码，其中控制器分别将具有公共用户数据的多个数据划分成用户数据和保证码，存储用户数据之一 在所述存储区域的预定单位的区域中，在所述存储区域的预定单位的区域中链接并存储伴随所述多个用户数据的每个所述保证码。

公开(公告)号：US20230185489A1

公开(公告)日：2023-06-15

申请号：US17900968

申请日：2022-09-01

Applicant: Hitachi, Ltd.

Inventor： Shugo OGAWA ,  Ryosuke TATSUMI ,  Yoshinori OHIRA ,  Hiroto EBARA ,  Junji OGAWA

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0647 ,  G06F3/0673 ,  G06F3/0604

Abstract: A first controller manages first mapping information for accessing data stored in a storage area, management of which is assigned to the first controller, and second mapping information for accessing data stored in a predetermined storage area, management of which is assigned to a second controller. The second controller, when having executed garbage collection on the predetermined storage area, changes mapping information to post-migration mapping information for accessing data after being migrated by the garbage collection. The first controller acquires the post-migration mapping information from the second controller, and updates the second mapping information using the post-migration mapping information when information in the second mapping information and is to be used for accessing the data in the predetermined storage area has been updated accompanying the garbage collection when the first controller accesses the data in the predetermined storage area after the garbage collection by using the second mapping information.

公开(公告)号：US20200097396A1

公开(公告)日：2020-03-26

申请号：US16495752

申请日：2017-08-23

Applicant: HITACHI, LTD. ,  HITACHI INFORMATION & TELECOMMUNICATION ENGINEERING, LTD.

Inventor： Koshi HOSHINO ,  Shigeo HOMMA ,  Junji OGAWA ,  Yoshinori OHIRA

IPC: G06F12/02 ,  G06F3/06

Abstract: An upper system of an NVM device transmits, to the NVM device, a write command that designates a logical address, the write command being associated with an expiration date corresponding to a data expiration date correlated with write target data. The NVM device correlates an expiration date correlated with the write command with a logical address specified from the write command. The NVM device writes pieces of data of which the remaining time which is the time to an expiration date belongs to the same remaining time range to the same physical storage area among the plurality of physical storage areas. The NVM device erases data from a physical storage area when the expiration dates of all pieces of data in the physical storage area have expired.

公开(公告)号：US20190073330A1

公开(公告)日：2019-03-07

申请号：US16093664

申请日：2016-09-26

Applicant: HITACHI, LTD.

Inventor： Yasuhiro IKEDA ,  Yutaka UEMATSU ,  Shungo OKABE ,  Akihiro INAMURA ,  Takahiko IWASAKI ,  Junji OGAWA

IPC: G06F13/40 ,  G06F13/16 ,  G06F12/02 ,  G06F3/06

Abstract: To increase the number of selectable chips without adding a signal line to a general purpose memory controller. A semiconductor storage device includes a memory controller, a plurality of memory chips, a selection unit which is connected to the memory controller and is connected with the plurality of memory chips to be able to select any one of the plurality of memory chips, and a switch unit which is connected to the memory controller and the selection unit. The memory controller and the selection unit are connected by a signal line for transmitting a first signal outputted from the memory controller and configured to select the memory chips. The memory controller and the switch unit are connected by a signal line for transmitting a second signal outputted from the memory controller and configured to select the memory chips.

公开(公告)号：US20180196622A1

公开(公告)日：2018-07-12

申请号：US15741600

申请日：2015-11-05

Applicant: HITACHI, LTD.

Inventor： Masatsugu OSHIMI ,  Junji OGAWA ,  Yoshihiro OIKAWA

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0652 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/16 ,  G06F2212/1036 ,  G06F2212/7211

Abstract: This nonvolatile memory device has a blockwise-erase nonvolatile memory including a plurality of physical areas, and also has a memory controller which transmits one of a plurality of types of commands to the nonvolatile memory. After an erase command to erase one of the physical areas has been transmitted, but before a response to that erase command is received, the memory controller determines whether to suspend the ongoing erasure of the physical area, on the basis of whether there is a command to be transmitted and/or on the basis of the degree of deterioration of the physical area being erased. If the determination is affirmative, the memory controller transmits a command to the nonvolatile memory to suspend the erasure.

公开(公告)号：US20180061498A1

公开(公告)日：2018-03-01

申请号：US15556680

申请日：2015-06-19

Applicant: Hitachi, Ltd.

Inventor： Yohei HAZAMA ,  Junji OGAWA ,  Kenta NINOSE

IPC: G11C16/26 ,  G11C16/34 ,  G11C11/56 ,  G06F11/10 ,  G06F3/06

CPC classification number: G11C16/26 ,  G06F3/067 ,  G06F3/0688 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1076 ,  G06F12/16 ,  G11C11/5642 ,  G11C16/349 ,  G11C2211/5648

Abstract: A flash memory controller is configured to hold a read pattern defining an order of selection of read options specifying a parameter value for a read from the flash memory chip. The flash memory controller is configured to execute error correction on data read from the flash memory chip in accordance with the read command. The flash memory controller is configured to designate a next read option specified in the read pattern to read the data from the flash memory chip in a case where all errors in the read data are not corrected by the error correction.

公开(公告)号：US20170010944A1

公开(公告)日：2017-01-12

申请号：US15113511

申请日：2014-01-29

Applicant: HITACHI, LTD.

Inventor： Hideo SAITO ,  Junji OGAWA ,  Hiroaki AKUTSU ,  Hideyuki KOSEKI ,  Atsushi KAWAMURA

IPC: G06F11/20 ,  G06F3/06

CPC classification number: G06F11/2094 ,  G06F3/0614 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0688 ,  G06F2201/805 ,  G06F2201/82

Abstract: A storage apparatus includes: a plurality of flash memory devices each including: a plurality of flash memory chips each including a plurality of physical blocks being data erasure units; and a flash controller configured to provide logical storage areas by associating at least one of the plurality of physical blocks with the logical storage areas; and a RAID controller configured to: manage a plurality of virtual drives each including a part of the logical storage areas provided by each of the plurality of flash memory devices; and control the plurality of virtual drives as a RAID group.

Abstract translation: 一种存储装置，包括：多个闪速存储器件，每个闪存器件包括：多个闪速存储器芯片，每个闪存芯片包括多个物理块，为数据擦除单元; 以及闪存控制器，被配置为通过将所述多个物理块中的至少一个与所述逻辑存储区域相关联来提供逻辑存储区域; 以及RAID控制器，被配置为：管理多个虚拟驱动器，每个虚拟驱动器包括由所述多个闪速存储器设备中的每一个提供的逻辑存储区域的一部分; 并将多个虚拟驱动器控制为RAID组。

公开(公告)号：US20150127896A1

公开(公告)日：2015-05-07

申请号：US14597454

申请日：2015-01-15

Applicant: HITACHI, LTD.

Inventor： Atsushi KAWAMURA ,  Junji OGAWA

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/065 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/0246 ,  G06F2212/1028 ,  G06F2212/1032 ,  G06F2212/7207 ,  Y02D10/13

Abstract: A storage system comprises a storage comprising a nonvolatile storage medium, and a storage control apparatus for inputting/outputting data to/from the storage. The storage control apparatus comprises a memory for storing management information, which is information used in inputting/outputting data to/from the storage, and a control part for controlling access to the storage. The control part stores the management information, which is stored in the memory, in the storage as a base image, and when the management information is updated subsequent to the base image being stored in the storage, creates a journal comprising information related to this update, and stores the journal in the storage as a journal group which is configured from multiple journals.

Abstract translation: 一种存储系统包括一个包括非易失性存储介质的存储器，以及用于向/从存储器输入/输出数据的存储控制装置。 存储控制装置包括用于存储管理信息的存储器，其是用于向/从存储器输入/输出数据的信息，以及用于控制对存储器的访问的控制部分。 控制部将存储在存储器中的管理信息作为基本图像存储在存储器中，并且当在存储在存储器中的基本映像之后更新管理信息时，创建包含与该更新相关的信息的日志 ，并将日记存储在存储中作为由多个日志配置的日志组。