公开(公告)号：US3641516A

公开(公告)日：1972-02-08

申请号：US3641516D

申请日：1969-09-15

Applicant: IBM

Inventor： CASTRUCCI PAUL P ,  GATES HARLAN R ,  HENLE ROBERT A ,  PRICER WILBUR DAVID ,  MORTON ROBERT M ,  MASON JOHN W ,  NORTH WILLIAM D

IPC: F22B21/06 ,  G11C17/06 ,  G11C17/14 ,  G11C17/16 ,  H01L23/525 ,  H01L27/00 ,  H01L27/102 ,  G11C11/36 ,  G11C17/00

CPC classification number: H01L27/1021 ,  F22B21/065 ,  G11C17/06 ,  G11C17/16 ,  H01L23/525 ,  H01L27/00 ,  H01L2924/0002 ,  Y10S148/055 ,  Y10S257/926 ,  H01L2924/00

Abstract: A read only memory having the capability of being written into once after manufacture. The cells of the memory are capable of being fused or permanently altered by directing a fusing current to the selected cells. The cell is a monolithic semiconductor device comprising a diode to be biased in a forward direction and a diode to be biased in the reverse direction structured so as to form back-to-back diodes. The reverse diode has a lower reverse breakdown voltage than the forward diode, and a metal connection, unconnected to any remaining circuit elements contacts the semiconductor device between diode junctions. The fusing current causes a metal-semiconductor alloy to form and short out the reverse diode.

Abstract translation: 一种只读存储器，具有在制造后被写入一次的能力。 存储器的单元能够通过将熔化电流引导到所选择的单元来融合或永久地改变。 电池是一个单片半导体器件，它包括一个正向偏置的二极管和一个反向偏置的二极管，以便形成背对背二极管。 反向二极管具有比正向二极管更低的反向击穿电压，并且未连接到任何剩余的电路元件的金属连接接触二极管接头之间的半导体器件。 熔断电流使金属半导体合金形成并短路反向二极管。

公开(公告)号：US3585464A

公开(公告)日：1971-06-15

申请号：US3585464D

申请日：1967-10-19

Applicant: IBM

Inventor： CASTRUCCI PAUL P ,  HESS MARTIN S ,  MAHERAS GEORGE ,  NORTH WILLIAM D ,  GROCHOWSKI EDWARD G

IPC: H01L21/822 ,  H01L21/331 ,  H01L21/74 ,  H01L21/8222 ,  H01L27/00 ,  H01L27/04 ,  H01L29/04 ,  H01L29/73 ,  H01L19/00

CPC classification number: H01L29/045 ,  H01L21/74 ,  H01L21/8222 ,  H01L27/00 ,  Y10S148/037 ,  Y10S148/049 ,  Y10S148/085 ,  Y10S148/115 ,  Y10S438/91 ,  Y10S438/973

Abstract: A semiconductor device and a method for fabricating the same which is composed of a monocrystalline semiconductor body having a surface crystallographic orientation substantially parallel to a plane and having a PN junction formed in the body. The body has an insulator coating, such as silicon dioxide, over the PN junction. The surface state density at the semiconductorinsulator interface is very low. This low density is believed to be a reason for the increased beta in the oriented material semiconductor device. Further, the device has a low defect density and few dopant precipitate sites even at high dopant levels. A monolithic integrated circuit structure composed of the monocrystalline semiconductor substrate having a surface crystallographic orientation substantially parallel to a plane with a plurality of semiconductor devices within the substrate is described. The devices are isolated from one another by PN junctions. The tolerance in a given isolated device, between the PN junction and the nearest region having a different conductivity is less than approximately 0.3 mils. This very close spacing allows substantially greater compactness of semiconductor devices within a monocrystalline semiconductor body than has ever been previously accomplished.

公开(公告)号：US3573974A

公开(公告)日：1971-04-06

申请号：US3573974D

申请日：1968-03-21

Applicant: IBM

Inventor： CASTRUCCI PAUL P ,  GROCHOWSKI EDWARD G

IPC: C23C16/12 ,  H01L21/00 ,  H01L23/485 ,  C23C11/02 ,  H01L7/00

CPC classification number: H01L21/00 ,  C23C16/12 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S438/913 ,  H01L2924/00

Abstract: A METHOD FOR FORMING ALUMINUM OHMIC CONTACTS AND CONDUCTIVE CONNECTORS ON SEMICONDUCTOR DEVICES HAVING SILICON DIOXIDE PASSIVATING MASKS COVERING PORTIONS OF A SEMICONDUCTOR SUBSTRATE. THE ALUMINUM CONTACTS AND CONNECTORS ARE FORMED BY THE DISPROPORTIONATION OF ALUMINUM MONO-HALIDE VAPOR IN THE PRESENCE OF THE SILICON DIOXIDE

MASKED SUBSTRATE. THE ALUMINUM FORMED BY THE DISPROPORTIONATION IS DEPOSITED AS A LAYER OVER THE MASKED SUBSTRATE. THEN, PORTIONS OF THE ALUMINUM LAYER ARE SELECTIVELY REMOVED TO LEAVE A PATTERN OHMIC CONTACTS AND CONDUCTIVE CONNECTORS.

公开(公告)号：US3508209A

公开(公告)日：1970-04-21

申请号：US3508209D

申请日：1966-03-31

Applicant: IBM

Inventor： AGUSTA BENJAMIN ,  BARDELL PAUL H ,  CASTRUCCI PAUL P ,  HENLE ROBERT A ,  PECORARO RAYMOND P

IPC: H01L27/08 ,  G11C11/411 ,  H03K3/286 ,  H03K3/288 ,  G11C5/04 ,  G11C11/40 ,  H01L19/00

CPC classification number: H03K3/288 ,  G11C11/4113 ,  H03K3/286

公开(公告)号：US3480841A

公开(公告)日：1969-11-25

申请号：US3480841D

申请日：1967-01-13

Applicant: IBM

Inventor： CASTRUCCI PAUL P ,  COLLINS ROBERT H ,  SHEPHEARD ROBERT G

IPC: H01L21/00 ,  H01L21/60 ,  H01L23/485 ,  H01L3/00 ,  H01L5/00

CPC classification number: H01L23/485 ,  H01L21/00 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/37147 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/00

Abstract: 1,193,532. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORP. 8 Jan., 1968 [13 Jan., 1967], No. 1001/68. Heading H1K. [Also in Division C7] Electrical contact is made to a semi-conductor region with an impurity concentration of at least 1018 atoms cm. -3 by depositing first a film of chromium, aluminium or titanium and then a film of nickel, silver, copper or copper chromium alloy. In one embodiment an antimony-doped N+type silicon wafer carrying an epitaxial N type layer is first provided with a silicon oxide coating by heating in dry oxygen and then in steam, or by R.F. sputtering, or with a layer of silicon nitride or alumina. Base and emitter regions are then formed by successive diffusions of boron and phosphorus into the N layer using standard planar techniques, the second diffusion doping the emitter and collector contact region with 5 Î 10 20 atoms/c.c. of phosphorus. Aluminium base and emitter contacts are next provided by vapour deposition overall followed by form-etching and sintering. Glass is subsequently deposited over the contacted face of the wafer in two stages of R.F. sputtering each followed by a firing stage. The wafer is then inverted in an evacuated vapour deposition chamber and its back collector contact face coated with successive layers of chromium, copper and gold of specified thickness while the wafer is held at 200-250‹ C. Holes are next etched through the glass layer to expose the aluminium contacts upon which similar layers of Cr, Cu and Au are then deposited through masks followed by layers of lead-tin solder by means of which nickel-plated copper balls are attached to the contacts. Finally the completed elements are attached to silver palladium lands on an alumina mounting plate and the ball contacts connected via nickel-plated copper strips to adjacent lands using lead-tin solder. In alternative planar diode and transistor embodiments the outer layer of gold is omitted.

公开(公告)号：US3447984A

公开(公告)日：1969-06-03

申请号：US3447984D

申请日：1965-06-24

Applicant: IBM

Inventor： CASTRUCCI PAUL P ,  IM SAMUEL S

IPC: C23F1/02 ,  H01L21/00 ,  H01L23/29 ,  H01L23/485

CPC classification number: H01L23/291 ,  C23F1/02 ,  H01L21/00 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S148/043 ,  Y10S148/051 ,  Y10S148/106 ,  Y10S438/95 ,  H01L2924/00