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    Method for Patterning an Underlying Layer
    12.
    发明申请
    Method for Patterning an Underlying Layer 有权
    图形层叠方法

    公开(公告)号：US20160254161A1

    公开(公告)日：2016-09-01

    申请号：US15045923

    申请日：2016-02-17

    Applicant: IMEC VZW

    Inventor： Boon Teik Chan ,  Zheng Tao ,  Nadia Vandenbroeck ,  Safak Sayan

    IPC: H01L21/308 ,  H01L29/66

    CPC classification number: H01L21/3081 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L29/66795

    Abstract: A method for patterning an underlying layer is described, the method comprising providing a guiding layer on the underlying layer, the guiding layer comprising guiding structures and being substantially planar; providing a block-copolymer layer on the guiding layer; inducing phase separation of the block-copolymer layer in a regular pattern of structures of a first and a second polymer component, whereby one of the components aligns to the guiding structures, by chemo-epitaxy; thereafter, removing a first of the components of the block-copolymer layers completely, leaving a regular pattern of structures of the second component; providing a planarizing layer over the regular pattern of structures of the second component and the guiding layer; removing a portion of the planarizing layer, thereby leaving a regular pattern of structures of the planarizing layer at positions in between the structures of the second component, and exposing the structures of the second component; removing the structures of the second component, selectively with respect to the structures of the planarizing layer; and patterning the underlying layer, thereby using the structures of the planarizing layer as a mask.

    Abstract translation: 描述了用于图案化下层的方法，所述方法包括在下层上提供引导层，所述引导层包括引导结构并且基本上是平面的; 在引导层上提供嵌段共聚物层; 诱导嵌段共聚物层以第一和第二聚合物组分的规则形式的结构相分离，由此其中一种组分通过化学外延对准引导结构; 此后，完全去除嵌段共聚物层中的第一组分，留下第二组分的规则的结构图案; 在所述第二部件和所述引导层的结构的规则图案上提供平坦化层; 去除所述平坦化层的一部分，从而在所述第二部件的结构之间的位置处留下所述平坦化层的规则的结构图案，并暴露所述第二部件的结构; 相对于平坦化层的结构选择性地去除第二部件的结构; 并对底层进行图案化，由此使用平坦化层的结构作为掩模。

    Method for forming a semiconductor device
    15.
    发明授权
    Method for forming a semiconductor device 有权

    公开(公告)号：US12237371B2

    公开(公告)日：2025-02-25

    申请号：US17476747

    申请日：2021-09-16

    Applicant: IMEC VZW

    Inventor： Boon Teik Chan ,  Hans Mertens ,  Eugenio Dentoni Litta

    IPC: H01L29/06 ,  H01L29/786

    Abstract: A method for forming a semiconductor device is provided. The method comprises forming a device layer stack comprising an alternating sequence of lower sacrificial layers and channel layers, and a top sacrificial layer over the topmost channel layer, wherein the top sacrificial layer is thicker than each lower sacrificial layer; etching the top sacrificial layer to form a top sacrificial layer portion underneath the sacrificial gate structure; forming a first spacer on end surfaces of the top sacrificial layer portion; etching the channel and lower sacrificial layers while using the first spacer as an etch mask to form channel layer portions and lower sacrificial layer portions; etching the lower sacrificial layer portions to form recesses in the device layer stack, while the first spacer masks the end surfaces of the top sacrificial layer portion; and forming a second spacer in the recesses.

    Stacked SRAM Cell with a Dual-Side Interconnect Structure
    16.
    发明公开
    Stacked SRAM Cell with a Dual-Side Interconnect Structure 审中-公开

    公开(公告)号：US20240206145A1

    公开(公告)日：2024-06-20

    申请号：US18545760

    申请日：2023-12-19

    Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

    Inventor： Hsiao-Hsuan Liu ,  Shairfe Muhammad Salahuddin ,  Boon Teik Chan ,  Sujith Subramanian

    IPC: H10B10/00 ,  H01L23/528

    CPC classification number: H10B10/125 ,  H01L23/5286

    Abstract: The present disclosure relates to static random access memory (SRAM). In particular, the disclosure provides a stacked SRAM cell, and a method for fabricating the stacked SRAM cell. The stacked SRAM cell comprises two first transistor structures and two second transistor structures, which form a pair of cross-coupled inverters, an comprises one or two pass gate (PG) transistor structures. Further, the stacked SRAM cell comprises a first power rail and/or a second power rail arranged above the transistor structures, wherein the first power rail is connected by respective first vias to the first transistor structures from above, and/or the second power rail is connected by respective second vias to the second transistor structures from above. The SRAM cell also comprises one or two bit lines arranged below the PG transistor structures. Each bit line is connected by a respective third via to one PG transistor structure from below.

    METHOD FOR INTERCONNECTING A BURIED WIRING LINE AND A SOURCE/DRAIN BODY
    17.
    发明公开
    METHOD FOR INTERCONNECTING A BURIED WIRING LINE AND A SOURCE/DRAIN BODY 审中-公开

    公开(公告)号：US20240136225A1

    公开(公告)日：2024-04-25

    申请号：US18486370

    申请日：2023-10-12

    Applicant: IMEC VZW

    Inventor： Boon Teik Chan ,  Hans Mertens ,  Zsolt Tokei ,  Naoto Horiguchi

    IPC: H01L21/768 ,  H01L23/528 ,  H01L29/40

    CPC classification number: H01L21/76879 ,  H01L21/76802 ,  H01L23/5286 ,  H01L29/401

    Abstract: A method provided for interconnecting a buried wiring line and a source/drain body. The method includes: forming a fin structure on a substrate, the fin structure comprising at least one channel layer; forming a buried wiring line in a trench extending alongside the fin structure, wherein the buried wiring line is capped by a first insulating layer structure; forming a source/drain body on the at least one channel layer by epitaxy; forming a via hole in the first insulating layer structure to expose an upper surface of the buried wiring line; forming a metal via in the via hole; forming a second insulating layer structure over the first insulating layer structure, wherein a contact opening is defined in the second insulating layer structure to expose the source/drain body and an upper via portion of the metal via; and forming a source/drain contact in the contact opening, on the upper via portion and the source/drain body, thereby inter-connecting the buried wiring line and the source/drain body.

    Bit Cell for Static Random Access Memory
    18.
    发明公开
    Bit Cell for Static Random Access Memory 审中-公开

    公开(公告)号：US20230413504A1

    公开(公告)日：2023-12-21

    申请号：US18335310

    申请日：2023-06-15

    Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

    Inventor： Hsiao-Hsuan Liu ,  Shairfe Muhammad Salahuddin ,  Boon Teik Chan

    IPC: H10B10/00

    CPC classification number: H10B10/125

    Abstract: A bit cell for a Static Random-Access Memory (SRAM) is provided that includes first and second sets of transistors. Each set of transistors includes a respective pass-gate transistor and a respectively stacked complementary transistor pair of an upper transistor and a lower transistor. A source/drain terminal of a lower transistor of each set of transistors is connected to a respective first power supply extending in a first power supply track arranged below the lower transistor, whereas a source/drain terminal of an upper transistor of each set of transistors is connected to a respective second power supply extending in a second power supply track arranged above the upper transistor.

    Method for Forming a Stacked FET Device
    19.
    发明公开
    Method for Forming a Stacked FET Device 审中-公开

    公开(公告)号：US20230197830A1

    公开(公告)日：2023-06-22

    申请号：US18065353

    申请日：2022-12-13

    Applicant: IMEC VZW

    Inventor： Boon Teik Chan ,  Anne Vandooren ,  Naoto Horiguchi

    IPC: H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/40 ,  H01L21/8238

    CPC classification number: H01L29/66545 ,  H01L21/3213 ,  H01L21/31144 ,  H01L29/6656 ,  H01L29/66553 ,  H01L29/6653 ,  H01L29/66439 ,  H01L29/401 ,  H01L21/823807 ,  H01L21/823871 ,  H01L29/42392

    Abstract: A method for forming a stacked field-effect transistor device is provided. The method including: forming a bottom FET device comprising a bottom gate electrode arranged; forming a bonding layer of dielectric bonding material over the bottom FET device; and forming a top FET device on the bonding layer, including: forming a fin structure comprising a channel layer; etching through the bonding layer to form a bonding layer pattern comprising the dielectric bonding material underneath the fin structure; forming a dummy gate and a dummy gate spacer layer; forming cuts in the fin structure and the bonding layer pattern; forming recesses underneath a fin structure portion preserved underneath the dummy gate by laterally etching back side surface portions of a bonding layer pattern portion; removing the first spacer layer and subsequently forming a second spacer layer covering the side surfaces of the dummy gate and filling the recesses; removing the dummy gate selectively to the second spacer layer to form an upper gate cavity portion exposing the fin structure portion; forming a lower gate cavity portion exposing an upper surface of the bottom gate electrode, comprising removing the bonding layer pattern portion by subjecting the bonding layer pattern portion to an isotropic etching process via the upper gate cavity; and forming a gate electrode in the upper and lower gate cavity portions.

    VIA FORMATION IN AN INTEGRATED CIRCUIT
    20.
    发明公开
    VIA FORMATION IN AN INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20230197528A1

    公开(公告)日：2023-06-22

    申请号：US18054228

    申请日：2022-11-10

    Applicant: IMEC VZW

    Inventor： Boon Teik Chan ,  Dunja Radisic ,  Bilal Chehab

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L23/522

    CPC classification number: H01L21/823871 ,  H01L27/092 ,  H01L23/5226

    Abstract: A method for forming an integrated circuit. The method includes providing a semiconductor structure comprising: (i) two transistors, (ii) a gate on the channel of the transistor, (iii) contacts coupled to each transistor, (iv) a dielectric layer over the two transistors, the gate, and the contacts, (v) a first conductive line arranged within a first metallization level and extending along a first direction, (vi) a first conductive via connecting the first conductive line with a first contact of a transistor, and (vii) a second conductive via connecting the first conductive line with a second contact of a transistor. The method also includes recessing the first dielectric layer, providing spacers along the first conductive line, depositing a second dielectric layer on the first dielectric layer, forming an opening in the second dielectric layer and first dielectric layer, and providing a conductive material in the opening, thereby forming a third conductive via.

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