公开(公告)号：US20160254161A1

公开(公告)日：2016-09-01

申请号：US15045923

申请日：2016-02-17

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Zheng Tao ,  Nadia Vandenbroeck ,  Safak Sayan

IPC: H01L21/308 ,  H01L29/66

CPC classification number: H01L21/3081 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L29/66795

Abstract: A method for patterning an underlying layer is described, the method comprising providing a guiding layer on the underlying layer, the guiding layer comprising guiding structures and being substantially planar; providing a block-copolymer layer on the guiding layer; inducing phase separation of the block-copolymer layer in a regular pattern of structures of a first and a second polymer component, whereby one of the components aligns to the guiding structures, by chemo-epitaxy; thereafter, removing a first of the components of the block-copolymer layers completely, leaving a regular pattern of structures of the second component; providing a planarizing layer over the regular pattern of structures of the second component and the guiding layer; removing a portion of the planarizing layer, thereby leaving a regular pattern of structures of the planarizing layer at positions in between the structures of the second component, and exposing the structures of the second component; removing the structures of the second component, selectively with respect to the structures of the planarizing layer; and patterning the underlying layer, thereby using the structures of the planarizing layer as a mask.

Abstract translation: 描述了用于图案化下层的方法，所述方法包括在下层上提供引导层，所述引导层包括引导结构并且基本上是平面的; 在引导层上提供嵌段共聚物层; 诱导嵌段共聚物层以第一和第二聚合物组分的规则形式的结构相分离，由此其中一种组分通过化学外延对准引导结构; 此后，完全去除嵌段共聚物层中的第一组分，留下第二组分的规则的结构图案; 在所述第二部件和所述引导层的结构的规则图案上提供平坦化层; 去除所述平坦化层的一部分，从而在所述第二部件的结构之间的位置处留下所述平坦化层的规则的结构图案，并暴露所述第二部件的结构; 相对于平坦化层的结构选择性地去除第二部件的结构; 并对底层进行图案化，由此使用平坦化层的结构作为掩模。

公开(公告)号：US20160118295A1

公开(公告)日：2016-04-28

申请号：US14919226

申请日：2015-10-21

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Safak Sayan

IPC: H01L21/768 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L21/76816 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/76807

Abstract: A method for forming contact vias includes providing a substrate comprising a plurality of contact structures embedded in a first dielectric layer, the contacts abutting an upper surface of the first dielectric layer. The method also includes providing a second dielectric layer on the upper surface of the first dielectric layer, and providing contact vias in the second dielectric layer by patterning the second dielectric layer at least at positions corresponding to the contact structures, wherein patterning the second dielectric layer comprises using a DSA patterning technique.

Abstract translation: 用于形成接触孔的方法包括提供包括嵌入在第一介电层中的多个接触结构的衬底，所述接触件邻接第一电介质层的上表面。 该方法还包括在第一电介质层的上表面上提供第二电介质层，并且通过至少在对应于接触结构的位置处图案化第二电介质层，在第二电介质层中提供接触通孔，其中，图案化第二电介质层 包括使用DSA图案化技术。

公开(公告)号：US20170242335A1

公开(公告)日：2017-08-24

申请号：US15433397

申请日：2017-02-15

Applicant: IMEC VZW ,  KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&D

Inventor： Boon Teik Chan ,  Arjun Singh ,  Safak Sayan

IPC: G03F7/00 ,  H01L21/033

CPC classification number: G03F7/0002 ,  H01L21/0271 ,  H01L21/0337

Abstract: The present disclosure relates to a patterned structure, the structure comprising: i) a substrate, ii) a first layer on top of the substrate, comprising a filler material and a guiding material, wherein at least a top surface of the first layer comprises one or more zones of filler material and one or more zones of guiding material, and iii) a second layer on top of the first layer comprising a pattern of a first material, the pattern being either aligned or anti-aligned with the underlying one or more zones of guiding material; wherein the first material comprises a metal or a ceramic material and wherein the guiding material and the filler material either both comprise or both do not comprise the metal or ceramic material.

公开(公告)号：US09548208B2

公开(公告)日：2017-01-17

申请号：US15045923

申请日：2016-02-17

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Zheng Tao ,  Nadia Vandenbroeck ,  Safak Sayan

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/033 ,  H01L29/66

CPC classification number: H01L21/3081 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L29/66795

Abstract: A method for patterning an underlying layer is described, the method comprising providing a guiding layer on the underlying layer, the guiding layer comprising guiding structures and being substantially planar; providing a block-copolymer layer on the guiding layer; inducing phase separation of the block-copolymer layer in a regular pattern of structures of a first and a second polymer component, whereby one of the components aligns to the guiding structures, by chemo-epitaxy; thereafter, removing a first of the components of the block-copolymer layers completely, leaving a regular pattern of structures of the second component; providing a planarizing layer over the regular pattern of structures of the second component and the guiding layer; removing a portion of the planarizing layer, thereby leaving a regular pattern of structures of the planarizing layer at positions in between the structures of the second component, and exposing the structures of the second component; removing the structures of the second component, selectively with respect to the structures of the planarizing layer; and patterning the underlying layer, thereby using the structures of the planarizing layer as a mask.

Abstract translation: 描述了用于图案化下层的方法，所述方法包括在下层上提供引导层，所述引导层包括引导结构并且基本上是平面的; 在引导层上提供嵌段共聚物层; 诱导嵌段共聚物层以第一和第二聚合物组分的规则形式的结构相分离，由此其中一种组分通过化学外延对准引导结构; 此后，完全去除嵌段共聚物层中的第一组分，留下第二组分的规则的结构图案; 在所述第二部件和所述引导层的结构的规则图案上提供平坦化层; 去除所述平坦化层的一部分，从而在所述第二部件的结构之间的位置处留下所述平坦化层的规则的结构图案，并暴露所述第二部件的结构; 相对于平坦化层的结构选择性地去除第二部件的结构; 并对底层进行图案化，由此使用平坦化层的结构作为掩模。

公开(公告)号：US20160322461A1

公开(公告)日：2016-11-03

申请号：US15204853

申请日：2016-07-07

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Safak Sayan ,  Min-Soo Kim ,  Doni Parnell ,  Roel Gronheid

IPC: H01L29/10 ,  H01L29/78 ,  H01L21/308 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/1037 ,  H01L21/0273 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for producing fin structures, using Directed Self Assembly (DSA) lithographic patterning, in an area of a semiconductor substrate includes providing a semiconductor substrate covered with a shallow trench isolation (STI) layer stack on a side thereof; defining a fin area on that side of the substrate by performing a lithographic patterning step other than DSA, wherein the fin structures will be produced in the fin area; and producing the fin structures in the semiconductor substrate within the fin area according to a predetermined fin pattern using DSA lithographic patterning. The disclosure also relates to associated semiconductor structures.

公开(公告)号：US10303048B2

公开(公告)日：2019-05-28

申请号：US15433397

申请日：2017-02-15

Applicant: IMEC VZW ,  KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&D

Inventor： Boon Teik Chan ,  Arjun Singh ,  Safak Sayan

IPC: B32B7/00 ,  G03F7/00 ,  H01L21/033 ,  H01L21/027

Abstract: The present disclosure relates to a patterned structure, the structure comprising: i) a substrate, ii) a first layer on top of the substrate, comprising a filler material and a guiding material, wherein at least a top surface of the first layer comprises one or more zones of filler material and one or more zones of guiding material, and iii) a second layer on top of the first layer comprising a pattern of a first material, the pattern being either aligned or anti-aligned with the underlying one or more zones of guiding material; wherein the first material comprises a metal or a ceramic material and wherein the guiding material and the filler material either both comprise or both do not comprise the metal or ceramic material.

公开(公告)号：US09391141B2

公开(公告)日：2016-07-12

申请号：US14628608

申请日：2015-02-23

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Safak Sayan ,  Min-Soo Kim ,  Doni Parnell ,  Roel Gronheid

IPC: H01L21/308 ,  H01L29/10 ,  H01L29/06 ,  H01L21/762 ,  H01L21/027 ,  H01L21/311

CPC classification number: H01L29/1037 ,  H01L21/0273 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for producing fin structures, using Directed Self Assembly (DSA) lithographic patterning, in an area of a semiconductor substrate includes providing a semiconductor substrate covered with a shallow trench isolation (STI) layer stack on a side thereof; defining a fin area on that side of the substrate by performing a lithographic patterning step other than DSA, wherein the fin structures will be produced in the fin area; and producing the fin structures in the semiconductor substrate within the fin area according to a predetermined fin pattern using DSA lithographic patterning. The disclosure also relates to associated semiconductor structures.

Abstract translation: 在半导体衬底的区域中使用定向自组装（DSA）光刻图案来制造鳍结构的方法包括提供在其一侧上覆盖有浅沟槽隔离（STI）层堆叠的半导体衬底; 通过进行DSA以外的平版印刷图案化步骤，在所述基板的所述一侧上限定翅片区域，其中所述翅片结构将在所述翅片区域中产生; 以及使用DSA平版印刷图案，根据预定的散热片图案在散热片区域内的半导体衬底中制造翅片结构。 本公开还涉及相关联的半导体结构。

公开(公告)号：US20150243509A1

公开(公告)日：2015-08-27

申请号：US14628608

申请日：2015-02-23

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Safak Sayan ,  Min-Soo Kim ,  Doni Parnell ,  Roel Gronheid

IPC: H01L21/308 ,  H01L21/762 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/1037 ,  H01L21/0273 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for producing fin structures, using Directed Self Assembly (DSA) lithographic patterning, in an area of a semiconductor substrate includes providing a semiconductor substrate covered with a shallow trench isolation (STI) layer stack on a side thereof; defining a fin area on that side of the substrate by performing a lithographic patterning step other than DSA, wherein the fin structures will be produced in the fin area; and producing the fin structures in the semiconductor substrate within the fin area according to a predetermined fin pattern using DSA lithographic patterning. The disclosure also relates to associated semiconductor structures.

Abstract translation: 在半导体衬底的区域中使用定向自组装（DSA）光刻图案来制造鳍结构的方法包括提供在其一侧上覆盖有浅沟槽隔离（STI）层堆叠的半导体衬底; 通过进行DSA以外的平版印刷图案化步骤，在所述基板的所述一侧上限定翅片区域，其中所述翅片结构将在所述翅片区域中产生; 以及使用DSA平版印刷图案，根据预定的散热片图案在散热片区域内的半导体衬底中制造翅片结构。 本公开还涉及相关联的半导体结构。

公开(公告)号：US10192956B2

公开(公告)日：2019-01-29

申请号：US15204853

申请日：2016-07-07

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Safak Sayan ,  Min-Soo Kim ,  Doni Parnell ,  Roel Gronheid

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L21/027 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3065 ,  H01L29/66

Abstract: A method for producing fin structures, using Directed Self Assembly (DSA) lithographic patterning, in an area of a semiconductor substrate includes providing a semiconductor substrate covered with a shallow trench isolation (STI) layer stack on a side thereof; defining a fin area on that side of the substrate by performing a lithographic patterning step other than DSA, wherein the fin structures will be produced in the fin area; and producing the fin structures in the semiconductor substrate within the fin area according to a predetermined fin pattern using DSA lithographic patterning. The disclosure also relates to associated semiconductor structures.

公开(公告)号：US09905455B2

公开(公告)日：2018-02-27

申请号：US14919226

申请日：2015-10-21

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Safak Sayan

IPC: H01L21/4763 ,  H01L21/302 ,  H01L21/461 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L21/76816 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/76807

Abstract: A method for forming contact vias includes providing a substrate comprising a plurality of contact structures embedded in a first dielectric layer, the contacts abutting an upper surface of the first dielectric layer. The method also includes providing a second dielectric layer on the upper surface of the first dielectric layer, and providing contact vias in the second dielectric layer by patterning the second dielectric layer at least at positions corresponding to the contact structures, wherein patterning the second dielectric layer comprises using a DSA patterning technique.