公开(公告)号：US20230170300A1

公开(公告)日：2023-06-01

申请号：US18053636

申请日：2022-11-08

Applicant: IMEC VZW

Inventor： Zheng Tao ,  Stefan Decoster

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/3213

CPC classification number: H01L23/528 ,  H01L21/76885 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76877

Abstract: A method for forming an interconnection structure for a semiconductor device and an interconnection structure is disclosed. The method includes forming a conductive layer on an insulating layer and etching the conductive layer to form a first conductive line. Thereafter, a spacer is formed on a side wall of a first end portion of the first conductive line. The method further includes forming a second conductive line, parallel to the first conductive line, having a second end portion, wherein a side wall of the second end portion is arranged to abut the spacer such that the first and the second metal line are extending along the same line and separated by the spacer. A recess is formed in the second metal line, extending along a portion of the second metal line, and a second mask layer is arranged in the recess.

公开(公告)号：US10825682B2

公开(公告)日：2020-11-03

申请号：US15258838

申请日：2016-09-07

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Vasile Paraschiv ,  Efrain Altamirano Sanchez ,  Zheng Tao

IPC: H01L21/3065 ,  H01L21/308 ,  H01L21/306 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  B82Y40/00 ,  B82Y10/00 ,  H01L21/265 ,  H01L21/28

Abstract: A method for producing a pillar structure in a semiconductor layer, the method including providing a structure including, on a main surface, a semiconductor layer. A patterned hard mask layer stack is provided on the semiconductor layer that includes a first layer in contact with the semiconductor layer and a second layer overlying and in contact with the first layer. The semiconductor layer is etched using the patterned hard mask layer stack as a mask. The etching includes subjecting the structure to a first plasma thereby removing a first part of the semiconductor layer and at least a part of the second layer while preserving the first layer thereby, producing a first part of the pillar structure, thereafter; and subjecting the structure to a second plasma thereby removing a second part of the semiconductor layer thereby, producing a second part of the pillar structure.

公开(公告)号：US10790382B2

公开(公告)日：2020-09-29

申请号：US15845300

申请日：2017-12-18

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Silvia Armini ,  Elisabeth Camerotto ,  Zheng Tao

IPC: H01L29/66 ,  H01L29/775 ,  H01L29/10 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  B82Y10/00

Abstract: A method for forming horizontal nanowires, the method comprising providing a substrate comprising a dielectric layer and a fin structure comprising a portion protruding from the dielectric layer, the protruding portion being partially un-masked and comprising a multi-layer stack consisting of a layer of a first material stacked alternately and repeatedly with a layer of a second material and forming horizontal nanowires done by performing a cycle comprising removing selectively the first material up to the moment that a horizontal nanowire of the second material becomes suspended over a remaining portion of the partially un-masked protruding portion, forming a sacrificial layer on the remaining portion, while leaving the suspended horizontal nanowire uncovered, providing, selectively, a cladding layer on the suspended horizontal nanowire, and thereafter removing the sacrificial layer. The horizontal nanowires become suspended starting from the top and the cladding layer is removed, after the bottom horizontal nanowire becomes suspended.

公开(公告)号：US10128371B2

公开(公告)日：2018-11-13

申请号：US15292778

申请日：2016-10-13

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Clement Merckling ,  Zheng Tao

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/20 ,  H01L29/66 ,  H01L29/786

Abstract: A method for forming a semiconductor device is disclosed. The method includes providing a semiconductor substrate. The method also includes epitaxially growing on the semiconductor substrate a first part of a III-V semiconductor nanostructure. The method further includes covering the first part of the III-V semiconductor nanostructure with a layer of a first material. Additionally, the method includes removing a top portion of the layer of the first material. Still further, the method includes epitaxially growing on the first part of the III-V semiconductor nanostructure a second part of the III-V semiconductor nanostructure. The method additionally includes covering the second part of the III-V semiconductor nanostructure with a layer of a second material. The second material is different from the first material. Even further, the method includes removing a top portion of the layer of the second material.

公开(公告)号：US20180043283A1

公开(公告)日：2018-02-15

申请号：US15674438

申请日：2017-08-10

Applicant: IMEC VZW

Inventor： Zheng Tao ,  Boon Teik Chan ,  XiuMei Xu ,  Khashayar Babaei Gavan ,  Efrain Altamirano Sanchez

IPC: B01D15/10 ,  B01D53/04

CPC classification number: B01D15/10 ,  B01D53/0407 ,  B01D63/14 ,  B01L3/502753 ,  B01L2300/0896 ,  B81B2201/058 ,  B81B2201/10 ,  B81B2203/0315 ,  B81B2203/0338 ,  B81B2203/0346 ,  B81B2203/0384 ,  B81C1/00119 ,  C12M1/123 ,  C12M33/14

Abstract: A method for producing a structure including, on a main surface of a substrate, at least one elongated cavity having openings at opposing ends. The method includes providing a substrate having a main surface. On the main surface, a first pair of features are formed that protrude perpendicularly from the main surface. The features have elongated sidewalls and a top surface, are parallel to one another, are separated by a gap having a width s1 and a bottom area, and have a width w1 and a height h1. At least the main surface of the substrate and the first pair of features are brought in contact with a liquid, suitable for making a contact angle of less than 90° with the material of the elongated sidewalls and subsequently the substrate is dried.

公开(公告)号：US20170179281A1

公开(公告)日：2017-06-22

申请号：US15292778

申请日：2016-10-13

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Clement Merckling ,  Zheng Tao

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L29/20

CPC classification number: H01L29/7827 ,  H01L21/02538 ,  H01L21/02603 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/20 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/78642

Abstract: A method for forming a semiconductor device is disclosed. The method includes providing a semiconductor substrate. The method also includes epitaxially growing on the semiconductor substrate a first part of a III-V semiconductor nanostructure. The method further includes covering the first part of the III-V semiconductor nanostructure with a layer of a first material. Additionally, the method includes removing a top portion of the layer of the first material. Still further, the method include epitaxially growing on the first part of the III-V semiconductor nanostructure a second part of the III-V semiconductor nanostructure. The method additionally includes covering the second part of the III-V semiconductor nanostructure with a layer of a second material. The second material is different from the first material. Even further, the method includes removing a top portion of the layer of the second material.

公开(公告)号：US11824122B2

公开(公告)日：2023-11-21

申请号：US17208800

申请日：2021-03-22

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Waikin Li ,  Zheng Tao

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L29/0669 ,  H01L29/66545 ,  H01L29/66818

Abstract: A method for partially filling a space between two superimposed structures in a semiconductor device under construction is provided. The method includes the steps of: (a) providing the two superimposed structures having said space therebetween; (b) entirely filling said space with a thermoplastic material; (c) removing a first portion of the thermoplastic material present in the space, the first portion comprising at least part of a top surface of the thermoplastic material, thereby leaving in said space a remaining thermoplastic material having a height; and (d) heating up the remaining photosensitive thermoplastic material so as to reduce its height. A replacement metal gate process for forming a different gate stack on two superimposed transistor channels in a semiconductor device under construction as well as a semiconductor device under construction is also provided.

公开(公告)号：US20230207482A1

公开(公告)日：2023-06-29

申请号：US18068839

申请日：2022-12-20

Applicant: IMEC VZW

Inventor： Waikin Li ,  Zheng Tao ,  Min-Soo Kim

IPC: H01L23/544 ,  H01L29/78 ,  H01L29/775 ,  H01L29/423 ,  H01L29/06 ,  H01L21/66

CPC classification number: H01L23/544 ,  H01L29/7827 ,  H01L29/775 ,  H01L29/42392 ,  H01L29/0669 ,  H01L22/20

Abstract: A semiconductor structure includes a device area that includes a first structure in a first layer having a top surface above a top surface of the first layer, and a second structure in a second layer on top of the first layer, where the first structure is pinned in the second structure; an overlay metrology area for optically evaluating an overlay error between the second and first structure, including: a third structure in the first layer, having a top surface above the top surface of the first layer, a fourth structure in the second layer, where the combination of the third and fourth structures mimics the combination of the first structure and the second structures, and a fifth structure in the first layer, for use as a reference structure.

公开(公告)号：US20230046117A1

公开(公告)日：2023-02-16

申请号：US17884870

申请日：2022-08-10

Applicant: IMEC VZW

Inventor： Zheng Tao ,  Waikin Li

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/306 ,  H01L23/528 ,  H01L21/762

Abstract: A method includes forming a trench in a semiconductor layer of a device wafer and depositing a liner on the trench sidewalls. The liner is removed from the trench bottom, and the trench is deepened anisotropically to form an extension fully along the trench, or locally by applying a mask. The semiconductor material is removed outwardly from the extension by etching to create a cavity wider than the trench and below the liner. A space formed by the trench and cavity is filled with electrically conductive material to form a buried interconnect rail comprising a narrow portion in the trench and a wider portion in the cavity. The wider portion can be contacted by a TSV connection, enabling a contact area between the connection and buried rail. The etching forms a wider rail portion at a location remote from active devices formed on the front surface of the semiconductor layer.

公开(公告)号：US11430697B2

公开(公告)日：2022-08-30

申请号：US16843706

申请日：2020-04-08

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Zheng Tao ,  Efrain Altamirano Sanchez

IPC: H01L21/8234 ,  H01L21/027 ,  H01L29/66 ,  H01L21/033

Abstract: A method for forming a mask layer above a semiconductor fin structure is disclosed. In one aspect the method includes forming a first set of spacers and a second set of spacers arranged at the side surfaces of the first set of spacers, providing a first filler material between the second set of spacers, etching a top portion of the first filler material to form recesses between the second set of spacers, and providing a second filler material in the recesses, the second filler material forming a set of sacrificial mask lines. Further, the method includes recessing a top portion of at least the first set of spacers, providing a mask layer material between the sacrificial mask lines, and removing the sacrificial mask lines and the first filler material.