公开(公告)号：US20210193512A1

公开(公告)日：2021-06-24

申请号：US17081337

申请日：2020-10-27

Applicant: IMEC VZW

Inventor： Martin O'Toole ,  Zsolt Tokei ,  Christopher Wilson ,  Stefan Decoster

IPC: H01L21/768 ,  H01L23/538 ,  H01L21/033

Abstract: A method is provided for producing electrically conductive lines (23a, 23b), wherein spacers are deposited on a sacrificial structure present on a stack of layers, including a hardmask layer on top of a dielectric layer into which the lines are to be embedded, and an intermediate layer on top of the hardmask layer. A self-aligned litho-etch step is then performed to create an opening in the intermediate layer, the opening being self-aligned to the space between two adjacent sidewalls of the sacrificial structure. This self-aligned step precedes the deposition of spacers on the sacrificial structure, so that spacers are also formed on the transverse sidewalls of the opening, i.e. perpendicular to the spacers on the walls of the sacrificial structure. A blocking material is provided in the area of the bottom of the opening that is surrounded on all sides by spacers, thereby creating a block with a reduced size.

公开(公告)号：US20170256451A1

公开(公告)日：2017-09-07

申请号：US15451175

申请日：2017-03-06

Applicant: IMEC vzw

Inventor： Juergen Boemmels ,  Zsolt Tokei ,  Christopher Wilson

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295

Abstract: An interconnect structure and a method for forming it is disclosed. In one aspect, the method includes the steps of providing a first entity. The first entity includes a first set of line structures. The first set of line structures include a first set of conductive lines, and a first set of dielectric lines made of a first dielectric material and aligned with and overlaying the first set of conductive lines. The first entity also includes gaps separating the line structures and filled with a second dielectric material of such a nature that the first dielectric material can be selectively etched with respect to the second dielectric material. The method also includes providing a patterned mask on the first entity. The method further includes etching selectively the first dielectric material through the patterned mask so as to form one or more vias in the first dielectric material. The method also includes removing the patterned mask.

公开(公告)号：US20240170328A1

公开(公告)日：2024-05-23

申请号：US18514461

申请日：2023-11-20

Applicant: IMEC VZW

Inventor： Anshul Gupta ,  Zsolt Tokei ,  Stefan Decoster

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/7684 ,  H01L21/7685 ,  H01L21/76877

Abstract: A method includes forming and patterning a first dielectric over a substrate; covering the first dielectric with metal and planarizing the metal exposing a surface of the first dielectric and forming a first metal; forming a second dielectric over the first dielectric and the first metal; covering the second dielectric with metal and planarizing the metal exposing a surface of the second dielectric and forming a second metal; forming a mask over the second dielectric and the second metal; and transferring: a first sub-pattern of the mask into a first portion of the first metal to form a lower metal, a second sub-pattern of the mask into a first portion of the second metal and a second portion of the first metal to form a stacked metal, and a third sub-pattern of the mask into a second portion of the second metal to form an upper metal.

公开(公告)号：US20230197514A1

公开(公告)日：2023-06-22

申请号：US18066400

申请日：2022-12-15

Applicant: IMEC VZW

Inventor： Victor Hugo Vega Gonzalez ,  Bilal Chehab ,  Julien Ryckaert ,  Zsolt Tokei ,  Serge Biesemans ,  Naoto Horiguchi

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/32139 ,  H01L21/76885 ,  H01L23/5226 ,  H01L21/32136 ,  H01L27/092

Abstract: The disclosure relates to a metallization process for an integrated circuit. One example metallization process includes a method for forming an integrated circuit that includes providing a semiconductor structure having two transistor structures, a gate structure, electrically conductive contacts, a first electrically conductive line, a first electrically conductive via, a second electrically conductive via. The method further includes providing a planar dielectric material in contact with the first electrically conductive line, forming an opening in the planar dielectric material, filling the opening with a planar electrically conductive material, forming an electrically conductive layer arranged within a second metallization level, the electrically conductive layer being in physical contact with the planar dielectric material and in physical and electrical contact with the electrically conductive material, providing a hard mask comprising a set of parallel lines, and etching the electrically conductive layer and the planar electrically conductive material by using the hard mask lines as a mask.

公开(公告)号：US11270912B2

公开(公告)日：2022-03-08

申请号：US17110631

申请日：2020-12-03

Applicant: IMEC VZW

Inventor： Martin O'Toole ,  Christopher Wilson ,  Zsolt Tokei ,  Ryan Ryoung han Kim

IPC: H01L21/768

Abstract: Example embodiments relate to methods for forming via holes self-aligned with metal blocks on substrates. One embodiment includes a method where the substrate includes an interlayer dielectric layer. The method includes forming a metallic layer on the interlayer dielectric layer. The method also includes forming a dielectric layer on the metallic layer and forming a plurality of parallel spacer line structures on the dielectric layer. In addition, the method includes forming a sidewall oxide, a first sacrificial layer, and an opening in the first sacrificial layer. Further, the method includes etching the dielectric layer and removing the first sacrificial layer. Additionally, the method includes forming a second sacrificial layer, forming an opening in the second sacrificial layer, depositing a metal block on the metallic layer, and removing the second sacrificial layer. Still further, the method includes etching the metallic layer and the interlayer dielectric layer to form a via hole.

公开(公告)号：US20210183698A1

公开(公告)日：2021-06-17

申请号：US17110631

申请日：2020-12-03

Applicant: IMEC VZW

Inventor： Martin O'Toole ,  Christopher Wilson ,  Zsolt Tokei ,  Ryan Ryoung han Kim

IPC: H01L21/768

Abstract: Example embodiments relate to methods for forming via holes self-aligned with metal blocks on substrates. One embodiment includes a method where the substrate includes an interlayer dielectric layer. The method includes forming a metallic layer on the interlayer dielectric layer. The method also includes forming a dielectric layer on the metallic layer and forming a plurality of parallel spacer line structures on the dielectric layer. In addition, the method includes forming a sidewall oxide, a first sacrificial layer, and an opening in the first sacrificial layer. Further, the method includes etching the dielectric layer and removing the first sacrificial layer. Additionally, the method includes forming a second sacrificial layer, forming an opening in the second sacrificial layer, depositing a metal block on the metallic layer, and removing the second sacrificial layer. Still further, the method includes etching the metallic layer and the interlayer dielectric layer to form a via hole.

公开(公告)号：US20200185579A1

公开(公告)日：2020-06-11

申请号：US16706002

申请日：2019-12-06

Applicant: IMEC VZW

Inventor： Soeren Steudel ,  Zsolt Tokei ,  Paul Heremans

IPC: H01L33/58 ,  H01L27/15 ,  H01L33/62

Abstract: A Light Emitting Diode (LED) device, particularly a micro-LED (μLED) device, suitable for a μLED display is described. The LED device comprises a LED array with a plurality of LEDs 12. It also comprises at least one top contact and bottom contact electrically connected to the LED array. Further, it comprises a conductive structure arranged above the LED array and the top contact, respectively, and electrically connected to the top contact. The conductive structure is, regarding each LED of the LED array, configured to absorb a first part of the light emitted by the LED, and to pass a second part of the light emitted by the LED. An emission angle (beam angle) of the passed light is thereby smaller than an emission angle of the light emitted by the LED.

公开(公告)号：US10395978B2

公开(公告)日：2019-08-27

申请号：US15907118

申请日：2018-02-27

Applicant: IMEC VZW

Inventor： Basoene Briggs ,  Farid Sebaai ,  Juergen Boemmels ,  Zsolt Tokei ,  Christopher Wilson ,  Katia Devriendt

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/308

Abstract: The disclosed technology generally relates to semiconductor processing, and more particularly to patterning a target layer using a sacrificial structure. According to an aspect of the disclosed technology, a method of patterning a target layer comprises forming on the target layer a plurality of parallel material lines spaced apart such that longitudinal gaps exposing the target layer are formed between the material lines. The method additionally includes filling the gaps with a sacrificial material and forming a hole by removing the sacrificial material along a portion of one of the gaps, where the hole extends across the gap. The hole exposes the target layer in the gap. The method additionally includes filling the hole with a fill material to form a block portion extending across the gap. The method additionally includes removing, selectively to the material lines and the block portion, the sacrificial material from the target layer to expose the gaps, where the one of the gaps is interrupted in the longitudinal direction by the block portion. The method further includes transferring a pattern including the material lines and the block portion into the target layer.

公开(公告)号：US20180247863A1

公开(公告)日：2018-08-30

申请号：US15907118

申请日：2018-02-27

Applicant: IMEC VZW

Inventor： Basoene Briggs ,  Farid Sebaai ,  Juergen Boemmels ,  Zsolt Tokei ,  Christopher Wilson ,  Katia Devriendt

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139

Abstract: The disclosed technology generally relates to semiconductor processing, and more particularly to patterning a target layer using a sacrificial structure. According to an aspect of the disclosed technology, a method of patterning a target layer comprises forming on the target layer a plurality of parallel material lines spaced apart such that longitudinal gaps exposing the target layer are formed between the material lines. The method additionally includes filling the gaps with a sacrificial material and forming a hole by removing the sacrificial material along a portion of one of the gaps, where the hole extends across the gap. The hole exposes the target layer in the gap. The method additionally includes filling the hole with a fill material to form a block portion extending across the gap. The method additionally includes removing, selectively to the material lines and the block portion, the sacrificial material from the target layer to expose the gaps, where the one of the gaps is interrupted in the longitudinal direction by the block portion. The method further includes transferring a pattern including the material lines and the block portion into the target layer.

公开(公告)号：US09997458B2

公开(公告)日：2018-06-12

申请号：US14400769

申请日：2013-05-14

Applicant: IMEC VZW

Inventor： Laure Elisa Carbonell ,  Antony Premkumar Peter ,  Marc Schaekers ,  Sven Van Elshocht ,  Zsolt Tokei

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/321 ,  H01L23/528 ,  H01L21/285

CPC classification number: H01L23/53209 ,  H01L21/28518 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76886 ,  H01L21/76889 ,  H01L23/528 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53261 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Method for forming an interconnect structure, comprising the steps of: forming a recessed structure in a dielectric material on a substrate; at least partially filling said recessed structure with a metal chosen from the group consisting of copper, nickel and cobalt; introducing the substrate in a CVD reactor; bringing the substrate in the CVD reactor to a soak temperature and subsequently performing a soak treatment by supplying a germanium precursor gas to the CVD reactor at the soak temperature, thereby substantially completely converting the metal in the recessed structure to a germanide.