公开(公告)号：US10197255B2

公开(公告)日：2019-02-05

申请号：US15479733

申请日：2017-04-05

Applicant: Industrial Technology Research Institute

Inventor： Heng-Chieh Chien ,  Yu-Lin Chao ,  Wen-Fu Hsu ,  Chih-Ming Shen ,  Chia-Wei Jui ,  Yao-Shun Chen

IPC: F21V21/35 ,  F21V21/14 ,  F21V23/06 ,  F21V19/02 ,  F21V19/00 ,  H01R25/14 ,  F21Y115/15

Abstract: A rail-type organic light emitting diode lamp assembly is provided. The lamp assembly includes a lamp module, an annular member, a connector, a conductive member, and a rail module. The annular member includes a protrusion portion having a pair of indentations. The connector is connected to the annular member, and includes a through hole, a first end provided with a pair of ears and a second end provided with a pair of hooks. The conductive member is provided in the through hole and has a first end in contact with the annular conductive coil. The rail module is connected with the connector and includes a conductor in contact with a second end of the conductive member. The connector can be slidably hooked to the rail module through the hooks, and after the ears are inserted into the indentations, the annular member can be rotatable with respect to the connector.

公开(公告)号：US10051742B2

公开(公告)日：2018-08-14

申请号：US14964575

申请日：2015-12-10

Applicant: Industrial Technology Research Institute

Inventor： Shu-Jung Yang ,  Yu-Lin Chao ,  Heng-Chieh Chien ,  Chun-Kai Liu

IPC: H05K1/18 ,  H01L29/02 ,  H05K3/46

Abstract: A power module and a manufacturing method thereof are provided, and the power module includes a carrier substrate, an interconnection layer, a first chip, a second chip, a ceramic bonding substrate, a top interconnection layer and a lead frame. The interconnection layer is disposed on the carrier substrate. The first chip and the second chip are disposed on the interconnection layer, and electrically connected to the interconnection layer. The ceramic bonding substrate is disposed on the interconnection layer, and is disposed in between the first chip and the second chip so as to separate the first chip from the second chip. The top interconnection layer is disposed on the ceramic bonding substrate, covers the first chip and the second chip, and is electrically connected to the first chip and the second chip. The lead frame is disposed on the top interconnection layer and electrically connected to the top interconnection layer.

公开(公告)号：US20170171978A1

公开(公告)日：2017-06-15

申请号：US14964575

申请日：2015-12-10

Applicant: Industrial Technology Research Institute

Inventor： Shu-Jung Yang ,  Yu-Lin Chao ,  Heng-Chieh Chien ,  Chun-Kai Liu

IPC: H05K1/18 ,  H05K3/30 ,  H05K3/46 ,  H05K1/02 ,  H05K1/03

CPC classification number: H05K1/185 ,  H01L29/02 ,  H05K1/186 ,  H05K3/4605 ,  H05K2201/10 ,  H05K2201/10166

Abstract: A power module and a manufacturing method thereof are provided, and the power module includes a carrier substrate, an interconnection layer, a first chip, a second chip, a ceramic bonding substrate, a top interconnection layer and a lead frame. The interconnection layer is disposed on the carrier substrate. The first chip and the second chip are disposed on the interconnection layer, and electrically connected to the interconnection layer. The ceramic bonding substrate is disposed on the interconnection layer, and is disposed in between the first chip and the second chip so as to separate the first chip from the second chip. The top interconnection layer is disposed on the ceramic bonding substrate, covers the first chip and the second chip, and is electrically connected to the first chip and the second chip. The lead frame is disposed on the top interconnection layer and electrically connected to the top interconnection layer.

公开(公告)号：US09252054B2

公开(公告)日：2016-02-02

申请号：US14484970

申请日：2014-09-12

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Sheng-Tsai Wu ,  Heng-Chieh Chien ,  John H. Lau ,  Yu-Lin Chao ,  Wei-Chung Lo

IPC: H01L23/367 ,  H01L21/768 ,  H01L21/48 ,  H01L23/42 ,  H01L23/427 ,  H01L23/433 ,  H01L21/50 ,  H01L21/56 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18

CPC classification number: H01L21/76898 ,  H01L21/4882 ,  H01L21/50 ,  H01L21/563 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/4275 ,  H01L23/433 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16235 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/16153 ,  H01L2924/16251 ,  H01L2924/1659 ,  H01L2924/167 ,  H01L2924/16724 ,  H01L2924/16747 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: A thinned integrated circuit device and manufacturing process for the same are disclosed. The manufacturing process includes forming a through-silicon via (TSV) on a substrate, a first terminal of the TSV is exposed on a first surface of the substrate, disposing a bump on the first surface of the substrate to make the bump electrically connected with the TSV, disposing an integrated circuit chip (IC) on the bump so that a first side of the IC is connected to the bump, disposing a thermal interface material (TIM) layer on a second side of the IC opposite to the first side of the IC, attaching a heat-spreader cap on the IC by the TIM layer, and backgrinding a second surface of the substrate to expose the TSV to the second surface of the substrate while carrying the heat-spreader cap.

Abstract translation: 公开了一种薄型集成电路器件及其制造方法。 制造工艺包括在衬底上形成贯通硅通孔（TSV），将TSV的第一端子暴露在衬底的第一表面上，在衬底的第一表面上设置凸块以使凸块电连接到 所述TSV在所述突起上设置集成电路芯片（IC），使得所述IC的第一侧连接到所述凸块，在所述IC的第二侧的第二侧上设置热界面材料（TIM）层， IC，通过TIM层将散热器帽附接到IC上，并且背衬研磨衬底的第二表面以在承载散热器盖的同时将TSV暴露于衬底的第二表面。

公开(公告)号：US20130276464A1

公开(公告)日：2013-10-24

申请号：US13854139

申请日：2013-04-01

Applicant: Industrial Technology Research Institute

Inventor： Heng-Chieh Chien ,  Ming-Ji Dai ,  Sheng-Tsai Wu ,  Huey-Lin Hsieh ,  Jing-Yi Huang

IPC: G01K7/00 ,  F25B21/04

CPC classification number: G01K7/00 ,  F25B21/04 ,  G01K3/08 ,  H01L35/30 ,  H01L35/32

Abstract: A measurement method, a measurement apparatus, and a computer program product for measuring a thermoelectric module are provided. A temperature is provided to the thermoelectric module. A current is applied to the thermoelectric module to turn both sides of the thermoelectric module into a hot side and a cold side. The temperature of the hot side is higher than that of the cold side. A terminal voltage of the thermoelectric module, a hot side temperature of the hot side, and a cold side temperature of the cold side are measured at different time points. A thermoelectric relationship between the terminal voltages and differences between the hot side temperatures and the corresponding cold side temperatures is obtained according to the terminal voltages, the hot side temperatures, and the cold side temperatures. At least one first parameter of the thermoelectric module is estimated according to the thermoelectric relationship.

Abstract translation: 提供了一种用于测量热电模块的测量方法，测量装置和计算机程序产品。 向热电模块提供温度。 向热电模块施加电流以将热电模块的两侧转变成热侧和冷侧。 热侧的温度高于冷侧的温度。 在不同的时间点测量热电模块的端电压，热侧的热侧温度和冷侧的冷侧温度。 根据端子电压，热侧温度和冷侧温度，获得端子电压与热侧温度与相应的冷侧温度之间的差异的热电关系。 根据热电关系估计热电模块的至少一个第一参数。

公开(公告)号：US20130234325A1

公开(公告)日：2013-09-12

申请号：US13873249

申请日：2013-04-30

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Ming-Ji Dai ,  Ra-Min Tain ,  Chun-Hsien Chien ,  Heng-Chieh Chien ,  Sheng-Tsai Wu

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/11009 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1421 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00

Abstract: By adding particles of high thermal conductivity and low thermal expansion coefficient into the copper as a composite material and filling with the composite material into the through-via hole, the mismatch of the coefficient of thermal expansion and the stress of the through-silicon via are lowered and the thermal conductivity of the through-silicon via is increased.

Abstract translation: 通过将高导热性和低热膨胀系数的颗粒作为复合材料添加到铜中，并将复合材料填充到通孔中，热膨胀系数与贯穿硅通孔的应力的失配是 降低了通硅通孔的导热性。