公开(公告)号：US20230061293A1

公开(公告)日：2023-03-02

申请号：US17411919

申请日：2021-08-25

Applicant: Intel Corporation

Inventor： Sagar Upadhyay ,  Archana Tankasala ,  Aliasgar S. Madraswala ,  Shantanu Rajwade

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/08 ,  G11C16/24

Abstract: Systems, apparatuses and methods may provide for technology that conducts a pulse-verify loop sequence from a first program level in targeted NAND memory cells to a next-to-last program level in the memory cells, wherein the pulse-verify loop sequence includes an issuance of a program pulse and one or more verify pulses to the memory cells on a per program level basis, and wherein successive program pulses differ from one another by a gate step voltage amount. The technology may also issue a last level program pulse to the memory cells at a last program level, issue a single verify pulse to the memory cells after the last level program pulse, and issue a gate step pulse to the memory cells at a variable program level, wherein the variable program level differs from the last program level by an amount that is greater than the gate step voltage amount.

公开(公告)号：US20190278488A1

公开(公告)日：2019-09-12

申请号：US16271572

申请日：2019-02-08

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Yogesh B. Wakchaure ,  Camila Jaramillo ,  Trupti Bemalkhedkar

IPC: G06F3/06 ,  G11C16/22

Abstract: A disclosed example to use an erase-suspend feature on a memory device includes a host interface to receive a first erase command to perform an erase operation; and a control circuit to: based on the erase-suspend feature being enabled at the memory device, suspend the erase operation based on determining that a length of time equal to an erase segment duration value has elapsed, the length of time elapsed being relative to a start of an erase segment, and the erase segment duration value specified in a configuration parameter for the erase-suspend feature; perform a second memory operation when the erase operation is suspended; and after the second memory operation is complete, resume the erase operation based on receiving a second erase command from the memory host controller.

公开(公告)号：US10268578B1

公开(公告)日：2019-04-23

申请号：US15721237

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Shankar Natarajan ,  Aliasgar S. Madraswala ,  Wayne D. Tran

IPC: G06F3/06 ,  G06F12/0804

Abstract: In one embodiment, a nonvolatile memory of a component such as a storage drive preserves write data in the event of a write data programming failure in the memory. Write data is preserved in the event of cached writes by data preservation logic in registers and data recovery logic recovers the preserved data and outputs the recovered data from the storage drive. Other aspects are described herein.

公开(公告)号：US20190102097A1

公开(公告)日：2019-04-04

申请号：US15721351

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Xin Guo ,  Naveen Vittal Prabhu ,  Yu Du ,  Purval Shyam Sule

IPC: G06F3/06

Abstract: In one embodiment, an apparatus comprises a memory array and a controller. The controller is to receive a first read command specifying a read voltage offset profile identifier; identify a read voltage offset profile associated with the read voltage offset profile identifier, the read voltage offset profile comprising at least one read voltage offset; and perform a first read operation specified by the first read command using at least one read voltage adjusted according to the at least one read voltage offset of the read voltage offset profile.

公开(公告)号：US09851905B1

公开(公告)日：2017-12-26

申请号：US15280898

申请日：2016-09-29

Applicant: INTEL CORPORATION

Inventor： Anand S. Ramalingam ,  Pranav Kalavade ,  Aliasgar S. Madraswala

IPC: G11C7/00 ,  G06F3/06 ,  G06F12/0802

CPC classification number: G06F3/0611 ,  G06F3/0647 ,  G06F3/0659 ,  G06F3/0685 ,  G06F12/0802 ,  G06F13/16

Abstract: A non-volatile memory interface employs concurrent memory operations for read operation preemption and includes transaction control logic configured to resume a suspended write operation concurrently with at least a portion of the transfer of read data from a non-volatile memory for a read operation which preempted the write operation. Memory control logic of the memory interface is configured to issue to the write operation suspend logic, a write operation resume command. The transaction control logic may be further configured to automatically suspend performing of a write operation in response to receipt of a read command. The transaction control logic may also be configured to automatically resume a previously suspended write operation in response to completion of a preemptive read operation by the memory.

公开(公告)号：US11923016B2

公开(公告)日：2024-03-05

申请号：US17033082

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Sagar Upadhyay ,  Jiantao Zhou

IPC: G11C16/26 ,  G06F3/06 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/26 ,  G06F3/0611 ,  G11C16/10 ,  G11C16/3431 ,  G11C16/3495

Abstract: Systems, apparatuses and methods may provide for technology that resumes a program operation with respect to NAND memory during a first tier in response to a suspension counter reaching a first threshold and resumes the program operation with respect to the NAND memory during a second tier in response to the suspension counter reaching a second threshold. The technology may also resume the program operation with respect to the NAND memory during a third tier in response to the suspension counter reaching a third threshold. Additionally, the technology may service one or more read operations with respect to the NAND memory until the suspension counter reaches the first threshold during the first tier, until the suspension counter reaches the second threshold during the second tier, and until the suspension counter reaches the third threshold during the third tier.

公开(公告)号：US20220415380A1

公开(公告)日：2022-12-29

申请号：US17357466

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Naveen Prabhu Vittal Prabhu ,  Aliasgar S. Madraswala ,  Bharat Pathak ,  Binh Ngo ,  Netra Mahuli ,  Ahsanur Rahman

IPC: G11C11/4076 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4096

Abstract: Systems, apparatuses and methods may provide for technology that sends a first command to a NAND die, sends first address information to the NAND die, and sends a second command to the NAND die, wherein the first command and the second command define a first command sequence and wherein the first address information signal a beginning of a first asynchronous read request from a first plurality of planes. In one example, the technology also sends a second command sequence and second address information to the NAND die wherein the second command sequence signals an end of the first asynchronous read request.

公开(公告)号：US11138102B2

公开(公告)日：2021-10-05

申请号：US16726796

申请日：2019-12-24

Applicant: Intel Corporation

Inventor： Sagar S. Sidhpura ,  Yogesh B. Wakchaure ,  Aliasgar S. Madraswala ,  Fei Xue

IPC: G06F12/0882 ,  G06F12/02 ,  G06F9/38 ,  G06F13/16 ,  G06F9/54

Abstract: A method and apparatus to reduce read latency and improve read quality of service (Read QoS) for non-volatile memory, such as NAND array in a NAND device. For read commands that collide with an in-progress program array operation targeting the same program locations in a NAND array, the in-progress program is suspended and the controller allows the read command to read from the internal NAND buffer instead of waiting for the in-progress program to complete. For read commands queued during an in-progress program that is processing pre-reads in preparation for a program array operation, pre-read bypass allows the reads to be serviced between the pre-reads and before the program's array operation starts. In this manner, read commands can be serviced without suspending the in-progress program. Allowing internal NAND buffer reads and enabling pre-read bypass reduces read latency and improves Read QoS.

公开(公告)号：US10437512B2

公开(公告)日：2019-10-08

申请号：US15394261

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Feng Zhu ,  Aliasgar S. Madraswala ,  Xin Guo

IPC: G06F3/06 ,  G11C29/00 ,  G11C7/14 ,  G11C29/52

Abstract: Examples herein include techniques for flash page retirement following one or more defects in nonvolatile memory. In some examples, a storage controller may retire a first logical page in response to a first read error, and write data to the one or more NVM devices in a program-erase (P/E) cycle without a dummy page being programmed or generated for the retired first logical page. The storage controller may further retire a second logical page in response to a second read error, wherein the first logical page has a higher order than the second logical page in a same physical memory page.

公开(公告)号：US10430108B2

公开(公告)日：2019-10-01

申请号：US15721483

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Shankar Natarajan ,  Aliasgar S. Madraswala

IPC: G06F13/00 ,  G06F3/06 ,  G11C11/56 ,  G06F11/10 ,  G11C16/04

Abstract: A determination is made that data has to be moved internally within a non-volatile memory from a plurality of pages of a first type of storage media to a page of a second type of storage media. A first subset of the plurality of pages is copied from the first type of storage media to the page of the second type of storage media. Concurrently with the copying of the first subset of the plurality of pages, a second subset of the plurality of pages is copied from the first type of storage media to the page of the second type of storage media. In response to completion of the copying of the first subset and the second subset of the plurality of pages, it is determined that the copying of the data from the first type of storage media to the second type of storage media has completed.