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    Concurrent compute and ECC for in-memory matrix vector operations
    11.
    发明授权
    Concurrent compute and ECC for in-memory matrix vector operations 有权

    公开(公告)号：US11513893B2

    公开(公告)日：2022-11-29

    申请号：US17128414

    申请日：2020-12-21

    Applicant: Intel Corporation

    Inventor： Somnath Paul ,  Charles Augustine ,  Chen Koren ,  George Shchupak ,  Muhammad M. Khellah

    IPC: G06F11/00 ,  G06F11/10 ,  G06N3/08

    Abstract: A system includes a compute circuit that preemptively performs a computation on a data word before receiving an indication of data errors from an error checking and correction (ECC) circuit. The ECC circuit reads the data word from a memory array and performs error detection and error correction on the data word. The compute circuit reads the data word and performs the computation on the data word to generate an output value, without waiting for the ECC circuit to check and correct the data word. In response to error detection in the data word by the ECC circuit, the compute circuit delays outputting the output value until correction of the output value in accordance with the error detection by the ECC circuit.

    CONCURRENT COMPUTE AND ECC FOR IN-MEMORY MATRIX VECTOR OPERATIONS
    13.
    发明申请
    CONCURRENT COMPUTE AND ECC FOR IN-MEMORY MATRIX VECTOR OPERATIONS 有权

    公开(公告)号：US20210109809A1

    公开(公告)日：2021-04-15

    申请号：US17128414

    申请日：2020-12-21

    Applicant: Intel Corporation

    Inventor： Somnath Paul ,  Charles Augustine ,  Chen Koren ,  George Shchupak ,  Muhammad M. Khellah

    IPC: G06F11/10 ,  G06N3/08

    Abstract: A system includes a compute circuit that preemptively performs a computation on a data word before receiving an indication of data errors from an error checking and correction (ECC) circuit. The ECC circuit reads the data word from a memory array and performs error detection and error correction on the data word. The compute circuit reads the data word and performs the computation on the data word to generate an output value, without waiting for the ECC circuit to check and correct the data word. In response to error detection in the data word by the ECC circuit, the compute circuit delays outputting the output value until correction of the output value in accordance with the error detection by the ECC circuit.

    Neuromorphic computing device, memory device, system, and method to maintain a spike history for neurons in a neuromorphic computing environment
    15.
    发明授权
    Neuromorphic computing device, memory device, system, and method to maintain a spike history for neurons in a neuromorphic computing environment 有权

    公开(公告)号：US10586147B2

    公开(公告)日：2020-03-10

    申请号：US15273505

    申请日：2016-09-22

    Applicant: INTEL CORPORATION

    Inventor： Wei Wu ,  Charles Augustine ,  Somnath Paul

    IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08

    Abstract: Provided are a neuromorphic computing device, memory device, system, and method to maintain a spike history for neurons in a spiking neural network. A neural network spike history is generated in a memory device having an array of rows and columns of memory cells. There is one row of the rows for each of a plurality of neurons and columns for each of a plurality of time slots. Indication is made in a current column in the row of the memory cells for a firing neuron that a spike was fired. Indication is made in the current column in rows of memory cells of idle neurons that did not fire that a spike was not fired. Information in the array is used to determine a timing difference between a connected neuron and the firing neuron and to adjust a weight of the connecting synapse.

    Calibrated biasing of sleep transistor in integrated circuits
    17.
    发明授权
    Calibrated biasing of sleep transistor in integrated circuits 有权

    公开(公告)号：US10454476B2

    公开(公告)日：2019-10-22

    申请号：US16145598

    申请日：2018-09-28

    Applicant: Intel Corporation

    Inventor： Suyoung Bang ,  Muhammad Khellah ,  Charles Augustine ,  Pascal Meinerzhagen ,  Minki Cho

    IPC: H03K19/00

    Abstract: Embodiments include apparatuses, methods, and systems associated with biasing a sleep transistor (also referred to as a power gate transistor) in an integrated circuit. The sleep transistor may be coupled between a load circuit and a power rail, the sleep transistor to be on in an active mode to provide the supply voltage to the load circuit, and to be off in a sleep mode to disconnect the load circuit from the power rail. The bias circuit may be coupled to the gate terminal of the sleep transistor to provide a calibrated gate voltage to the gate terminal during the sleep mode. The calibrated gate voltage may be based on a subthreshold leakage current and a gate-induced drain leakage (GIDL) current of the sleep transistor or a replica sleep transistor designed to replicate the leakage current of the sleep transistor. Other embodiments may be described and claimed.

    CALIBRATED BIASING OF SLEEP TRANSISTOR IN INTEGRATED CIRCUITS
    18.
    发明申请
    CALIBRATED BIASING OF SLEEP TRANSISTOR IN INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：US20190044512A1

    公开(公告)日：2019-02-07

    申请号：US16145598

    申请日：2018-09-28

    Applicant: Intel Corporation

    Inventor： Suyoung Bang ,  Muhammad Khellah ,  Charles Augustine ,  Pascal Meinerzhagen ,  Minki Cho

    IPC: H03K19/00

    CPC classification number: H03K19/0016 ,  H03K19/0013

    Abstract: Embodiments include apparatuses, methods, and systems associated with biasing a sleep transistor (also referred to as a power gate transistor) in an integrated circuit. The sleep transistor may be coupled between a load circuit and a power rail, the sleep transistor to be on in an active mode to provide the supply voltage to the load circuit, and to be off in a sleep mode to disconnect the load circuit from the power rail. The bias circuit may be coupled to the gate terminal of the sleep transistor to provide a calibrated gate voltage to the gate terminal during the sleep mode. The calibrated gate voltage may be based on a subthreshold leakage current and a gate-induced drain leakage (GIDL) current of the sleep transistor or a replica sleep transistor designed to replicate the leakage current of the sleep transistor. Other embodiments may be described and claimed.

    FLIP-FLOP CIRCUIT WITH LOW-LEAKAGE TRANSISTORS
    19.
    发明申请
    FLIP-FLOP CIRCUIT WITH LOW-LEAKAGE TRANSISTORS 有权

    公开(公告)号：US20180181175A1

    公开(公告)日：2018-06-28

    申请号：US15392559

    申请日：2016-12-28

    Applicant: Intel Corporation

    Inventor： Charles Augustine ,  Rafael Rios ,  Somnath Paul ,  Muhammad M. Khellah

    IPC: G06F1/26 ,  H03K3/356 ,  H03K3/012 ,  G06F1/32

    Abstract: Embodiments include apparatuses, methods, and systems for a flip-flop circuit with low-leakage transistors. The flip-flop circuit may be coupled to a logic circuit of an integrated circuit to store data for the logic circuit when the logic circuit is in a sleep state. The flip-flop circuit may pass a data signal for the logic circuit along a signal path. A capacitor may be coupled between the signal path and ground to store a value of the data signal when the logic circuit is in the sleep state. A low-leakage transistor, such as an IGZO transistor, may be coupled between the capacitor and the signal path and may selectively turn on when the logic circuit transitions from the active state to the sleep state to store the value of the data signal in the capacitor. Other embodiments may be described and claimed.

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