中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

47 records (took 0.02 seconds)

    LOWER-POWER SCRAMBLING WITH IMPROVED SIGNAL INTEGRITY
    11.
    发明申请
    LOWER-POWER SCRAMBLING WITH IMPROVED SIGNAL INTEGRITY 有权
    具有改进的信号完整性的下功率SCRAMBLING

    公开(公告)号：US20160188523A1

    公开(公告)日：2016-06-30

    申请号：US14583623

    申请日：2014-12-27

    Applicant: Intel Corporation

    Inventor： Ee Loon Teoh ,  Eng Hun Ooi ,  Christopher P. Mozak ,  Brian R. McFarlane

    IPC: G06F13/42 ,  G06F13/28

    CPC classification number: G06F13/4282 ,  G06F13/1668 ,  G06F13/28 ,  G06F21/79 ,  Y02D10/14 ,  Y02D10/151

    Abstract: An I/O interface supports scrambling, where the scrambling can include nonlinear scrambling of the scrambling code, or dynamic bus inversion of the scrambling code, or selective switching of selected bits of the scrambling code, or a combination of these. The transmitting device includes a scrambler and the receiving device includes a descrambler. Both the scrambler and the descrambler generate a linear feedback scrambling code modified by applying one or more of the techniques mentioned above. The modified scrambling code may cause fewer than half of the scrambled output bits to be toggled with respect to a previous scrambled output. The scrambler applies the modified scrambling code to a signal to transmit. The descrambler applies the modified scrambling code to a received signal.

    Abstract translation: I / O接口支持加扰，其中加扰可以包括扰码的非线性加扰或扰码的动态总线反转，或扰码的选定位的选择性切换，或这些的组合。 发送设备包括加扰器，并且接收设备包括解扰器。 加扰器和解扰器都产生通过应用上述一种或多种技术修改的线性反馈扰码。 经修改的扰码可能导致少于一半的加扰输出比特相对于先前的加扰输出被切换。 扰频器将修改的扰码应用于要发送的信号。 解扰器将修改的扰码应用于接收信号。

    DISABLING A COMMAND ASSOCIATED WITH A MEMORY DEVICE
    13.
    发明申请
    DISABLING A COMMAND ASSOCIATED WITH A MEMORY DEVICE 有权
    禁用与存储设备相关的命令

    公开(公告)号：US20150277790A1

    公开(公告)日：2015-10-01

    申请号：US14230338

    申请日：2014-03-31

    Applicant: Intel Corporation

    Inventor： Christopher P. Mozak ,  Kuljit S. Bains

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0634 ,  G06F3/0673 ,  G06F3/068 ,  G06F11/2094 ,  G06F2201/805 ,  G11C7/1045 ,  G11C7/24 ,  G11C29/025 ,  G11C29/46 ,  G11C29/50012 ,  G11C29/70 ,  G11C29/76 ,  G11C29/83

    Abstract: In an embodiment, a memory device may contain device processing logic and a mode register. The mode register may a register that may specify a mode of operation of the memory device. A field in the mode register may hold a value that may indicate whether a command associated with the memory device is disabled. The value may be held in the field until either the memory device is power-cycled or reset. The device processing logic may acquire an instance of the command. The device processing logic may determine whether the command is disabled based on the value held by the mode register. The device processing logic may not execute the instance of the command if the device processing logic determines the command is disabled. If the device processing logic determines the command is not disabled, the device processing logic may execute the instance of the command.

    Abstract translation: 在一个实施例中，存储器设备可以包含设备处理逻辑和模式寄存器。 模式寄存器可以是可以指定存储器件的操作模式的寄存器。 模式寄存器中的字段可以保存可以指示与存储器设备相关联的命令是否被禁用的值。 该值可以保持在现场，直到存储器件被上电或复位为止。 设备处理逻辑可以获取命令的实例。 设备处理逻辑可以基于模式寄存器保持的值来确定该命令是否被禁用。 如果设备处理逻辑确定该命令被禁用，则设备处理逻辑可能不执行该命令的实例。 如果设备处理逻辑确定命令未被禁止，则设备处理逻辑可以执行该命令的实例。

    Efficiently training memory device chip select control
    15.
    发明授权
    Efficiently training memory device chip select control 有权

    公开(公告)号：US10416912B2

    公开(公告)日：2019-09-17

    申请号：US15721516

    申请日：2017-09-29

    Applicant: Intel Corporation

    Inventor： Tonia G. Morris ,  Christopher P. Mozak ,  Christopher E. Cox

    IPC: G06F3/06 ,  G11C11/4076 ,  G11C8/12 ,  G11C29/00 ,  G11C29/02

    Abstract: A chip select training mode (CSTM) enables a memory subsystem to train a chip select signal separately from command bus training. A memory device and a memory controller can connect via a command bus including a chip select signal line. Instead of training the chip select along with other signal lines of the command bus, a CSTM mode enables the memory subsystem to more accurately train the chip select. The memory device can be triggered for CSTM mode with a command, and then train voltage margining for the CS signal line to align chip select signaling with the memory subsystem clock signal.

    Row hammer refresh command
    17.
    发明授权
    Row hammer refresh command 有权

    公开(公告)号：US10210925B2

    公开(公告)日：2019-02-19

    申请号：US15835050

    申请日：2017-12-07

    Applicant: Intel Corporation

    Inventor： Kuljit S. Bains ,  John B. Halbert ,  Christopher P. Mozak ,  Theodore Z. Schoenborn ,  Zvika Greenfield

    IPC: G06F12/00 ,  G11C11/4091 ,  G11C11/406 ,  G06F3/06

    Abstract: A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

    Disabling a command associated with a memory device
    19.
    发明授权
    Disabling a command associated with a memory device 有权
    禁用与存储设备关联的命令

    公开(公告)号：US09542123B2

    公开(公告)日：2017-01-10

    申请号：US14952324

    申请日：2015-11-25

    Applicant: Intel Corporation

    Inventor： Christopher P. Mozak ,  Kuljit S. Bains

    IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0634 ,  G06F3/0673 ,  G06F3/068 ,  G06F11/2094 ,  G06F2201/805 ,  G11C7/1045 ,  G11C7/24 ,  G11C29/025 ,  G11C29/46 ,  G11C29/50012 ,  G11C29/70 ,  G11C29/76 ,  G11C29/83

    Abstract: In an embodiment, a memory device may contain device processing logic and a mode register. The mode register may a register that may specify a mode of operation of the memory device. A field in the mode register may hold a value that may indicate whether a command associated with the memory device is disabled. The value may be held in the field until either the memory device is power-cycled or reset. The device processing logic may acquire an instance of the command. The device processing logic may determine whether the command is disabled based on the value held by the mode register. The device processing logic may not execute the instance of the command if the device processing logic determines the command is disabled. If the device processing logic determines the command is not disabled, the device processing logic may execute the instance of the command.

    Abstract translation: 在一个实施例中，存储器设备可以包含设备处理逻辑和模式寄存器。 模式寄存器可以是可以指定存储器件的操作模式的寄存器。 模式寄存器中的字段可以保存可以指示与存储器设备相关联的命令是否被禁用的值。 该值可以保持在现场，直到存储器件被上电或复位为止。 设备处理逻辑可以获取命令的实例。 设备处理逻辑可以基于模式寄存器保持的值来确定该命令是否被禁用。 如果设备处理逻辑确定该命令被禁用，则设备处理逻辑可能不执行该命令的实例。 如果设备处理逻辑确定命令未被禁止，则设备处理逻辑可以执行该命令的实例。

    I/O driver transmit swing control
    20.
    发明授权
    I/O driver transmit swing control 有权
    I / O驱动器发送摆幅控制

    公开(公告)号：US09374004B2

    公开(公告)日：2016-06-21

    申请号：US13931604

    申请日：2013-06-28

    Applicant: Intel Corporation

    Inventor： Christopher P. Mozak ,  Ritesh B. Trivedi ,  James A. McCall ,  Aaron Martin

    IPC: H03K19/0175 ,  H03K19/0185 ,  H02M3/158 ,  G11C29/02 ,  G11C7/10 ,  H04L25/02

    CPC classification number: H02M3/158 ,  G11C7/1057 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028 ,  G11C2207/105 ,  H04L25/0276 ,  H04L25/029

    Abstract: A transmission line interface circuit includes a voltage regulator to control a voltage swing of the transmission line interface circuit for signal transmission. The transmission line interface circuit includes complementary driver elements, including a p-type driver element to pull up the transmission line in response to a logic high, and an n-type driver element to pull down the transmission line in response to a logic low. The voltage regulator is coupled between one of the driver elements and a respective voltage reference to reduce a voltage swing of the transmission line interface circuit.

    Abstract translation: 传输线接口电路包括用于控制用于信号传输的传输线接口电路的电压摆幅的电压调节器。 传输线接口电路包括互补驱动器元件，包括响应于逻辑高来上拉传输线的p型驱动器元件，以及响应于逻辑低来拉低传输线的n型驱动器元件。 电压调节器耦合在驱动器元件之一和相应的电压基准之间，以减小传输线接口电路的电压摆幅。

Patent Agency Ranking