中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

28 records (took 0.02 seconds)

    Technology For Dynamically Grouping Threads For Energy Efficiency
    12.
    发明申请
    Technology For Dynamically Grouping Threads For Energy Efficiency 有权

    公开(公告)号：US20210055958A1

    公开(公告)日：2021-02-25

    申请号：US16547767

    申请日：2019-08-22

    Applicant: Intel Corporation

    Inventor： Deepak Samuel Kirubakaran ,  Vijay Dhanraj ,  Russell Jerome Fenger ,  Hisham Abu-Salah ,  Eliezer Weissmann

    IPC: G06F9/48 ,  G06F1/3296

    Abstract: A data processing system with technology for dynamically grouping threads includes a machine-readable medium and first and second cores, each with multiple logical processors (LPs). The system also comprises an operating system which, when executed, enables the system to select an LP to receive a new low-priority thread and to assign the new low-priority thread to the selected LP. The operation of selecting an LP to receive the new low-priority thread comprises, when the first core has multiple idle LPs, automatically determining whether the second core has an idle LP and a busy LP that is executing a current low-priority thread. In response to determining that the second core has an idle LP and a busy LP that is executing a current low-priority thread, the system automatically selects the idle LP in the second core to receive the new low-priority thread. Other embodiments are described and claimed.

    METHODS, SYSTEMS, AND APPARATUSES FOR DYNAMIC SIMULTANEOUS MULTI-THREADING (SMT) SCHEDULING TO MAXIMIZE PROCESSOR PERFORMANCE ON HYBRID PLATFORMS
    15.
    发明公开
    METHODS, SYSTEMS, AND APPARATUSES FOR DYNAMIC SIMULTANEOUS MULTI-THREADING (SMT) SCHEDULING TO MAXIMIZE PROCESSOR PERFORMANCE ON HYBRID PLATFORMS 审中-公开

    公开(公告)号：US20240220446A1

    公开(公告)日：2024-07-04

    申请号：US18149072

    申请日：2022-12-30

    Applicant: Intel Corporation

    Inventor： Deepak Samuel Kirubakaran ,  Rajshree Chabukswar ,  Zhongsheng Wang ,  Russell Fenger ,  Asit Kumar Verma ,  DK Deepika ,  Yevgeni Sabin ,  Daniel J. Rogers ,  Cameron T. Rieck

    IPC: G06F15/80 ,  G06F9/48

    CPC classification number: G06F15/80 ,  G06F9/48

    Abstract: Techniques for implementing dynamic simultaneous multi-threading (SMT) scheduling on a hybrid processor platforms are described. In certain examples, a hardware processor includes a first plurality of physical processor cores of a first type to implement a plurality of logical processor cores of the first type; a second plurality of physical processor cores of a second type, wherein each core of the second type is to implement a plurality of logical processor cores of the second type; and circuitry to: determine if a set of threads of a foreground application is to use more than a lower threshold (e.g., a threshold number (e.g., one) of logical processor cores) and less than or equal to an upper threshold (e.g., a total number of the first plurality of physical processor cores of the first type and the second plurality of physical processor cores of the second type), and disable a second logical core of a physical processor core of the second type, and not disable a first logical core of the physical processor core of the second type, in response to a determination that the set of threads of the foreground application is to use more than the lower threshold number of logical processor cores and less than or equal to the upper threshold (e.g., the total number of the first plurality of physical processor cores of the first type and the second plurality of physical processor cores of the second type).

    ENERGY-EFFICIENT CORE VOLTAGE SELECTION APPARATUS AND METHOD
    16.
    发明申请
    ENERGY-EFFICIENT CORE VOLTAGE SELECTION APPARATUS AND METHOD 有权

    公开(公告)号：US20220058029A1

    公开(公告)日：2022-02-24

    申请号：US17131547

    申请日：2020-12-22

    Applicant: Intel Corporation

    Inventor： Noor Mubeen ,  Ashraf H. Wadaa ,  Andrey Gabdulin ,  Russell Fenger ,  Deepak Samuel Kirubakaran ,  Marc Torrant ,  Ryan Thompson ,  Georgina Saborio Dobles ,  Lingjing Zeng

    IPC: G06F9/4401 ,  G06F9/50 ,  G06F9/38

    Abstract: A processor core energy-efficiency core ranking scheme akin to a favored core in a multi-core processor system. The favored core is the energy-efficient core that allows an SoC to use the core with the lowest Vmin for energy-efficiency. Such Vmin values may be fused in appropriate registers or stored in NVM during HVM. An OS scheduler achieves optimal energy performance using the core ranking information to schedule certain applications on the core with lowest Vmin. A bootstrap flow identifies a bootstrap processor core (BSP) as the most energy efficiency core of the SoC and assigns that core the lowest APIC ID value according to the lowest Vmin. Upon reading the fuses or NVM, the microcode/BIOS calculates and ranks the cores. As such, microcode/BIOS calculates and ranks core APIC IDs based on efficiency around LFM frequencies. Based on the calculated and ranked cores, the microcode or BIOS transfers BSP ownership to the most efficiency core.

Patent Agency Ranking