公开(公告)号：US20230197812A1

公开(公告)日：2023-06-22

申请号：US17553397

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Anand Murthy ,  Prashant Majhi ,  Glenn Glass

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/786 ,  H01L29/06 ,  H01L29/04 ,  H01L21/8238

CPC classification number: H01L29/42392 ,  H01L27/092 ,  H01L29/78696 ,  H01L29/0665 ,  H01L29/045 ,  H01L21/823807

Abstract: An integrated circuit structure includes a substrate, a first device above a first section of the substrate, and a second device above a second section of the substrate. The first device includes a first source region and a first drain region, and a first body extending laterally between the first source and first drain regions. In an example, the first body includes silicon with crystalline orientation described by Miller index of (100). The second device includes a second source region and a second drain region, and a second body extending laterally between the second source and second drain regions. In an example, the second body includes silicon with crystalline orientation described by Miller index of (110).

公开(公告)号：US20230197724A1

公开(公告)日：2023-06-22

申请号：US17557517

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Anand Murthy ,  Glenn Glass ,  Rushabh Shah ,  Susmita Ghose

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/66545 ,  H01L29/66742

Abstract: An integrated circuit structure includes a first non-planar semiconductor device and a second non-planar semiconductor device. The first non-planar semiconductor device includes a first body, a first gate structure at least in part wrapped around the first body, and a first source region and a first drain region. The first body extends laterally between the first source and first drain regions. The second non-planar semiconductor device comprises a second body, a second gate structure at least in part wrapped around the second body, and a second source region and a second drain region. The second body extends laterally between the second source and second drain regions. In an example, a first height of the first body is at least 5% different from a second height of the second body. Each of the first and second bodies can be, for instance, a nanoribbon, nanosheet, or nanowire.

公开(公告)号：US11450739B2

公开(公告)日：2022-09-20

申请号：US16131520

申请日：2018-09-14

Applicant: INTEL CORPORATION

Inventor： Glenn Glass ,  Anand Murthy ,  Cory Bomberger ,  Tahir Ghani ,  Jack Kavalieros ,  Siddharth Chouksey ,  Seung Hoon Sung ,  Biswajeet Guha ,  Ashish Agrawal

IPC: H01L29/06 ,  H01L21/82 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/161 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor structure has a substrate including silicon and a layer of relaxed buffer material on the substrate with a thickness no greater than 300 nm. The buffer material comprises silicon and germanium with a germanium concentration from 20 to 45 atomic percent. A source and a drain are on top of the buffer material. A body extends between the source and drain, where the body is monocrystalline semiconductor material comprising silicon and germanium with a germanium concentration of at least 30 atomic percent. A gate structure is wrapped around the body.

公开(公告)号：US11437472B2

公开(公告)日：2022-09-06

申请号：US16022510

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Siddharth Chouksey ,  Glenn Glass ,  Anand Murthy ,  Harold Kennel ,  Jack T. Kavalieros ,  Tahir Ghani ,  Ashish Agrawal ,  Seung Hoon Sung

IPC: H01L31/072 ,  H01L31/109 ,  H01L29/165 ,  H01L21/8234 ,  H01L29/06 ,  H01L27/088

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

公开(公告)号：US10672868B2

公开(公告)日：2020-06-02

申请号：US15778724

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Karthik Jambunathan ,  Glenn Glass ,  Anand Murthy ,  Jun Sung Kang ,  Seiyon Kim

IPC: H01L29/06 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/08 ,  H01L29/786 ,  H01L29/423

Abstract: Methods of forming self-aligned nanowire spacer structures are described. An embodiment includes forming a channel structure comprising a first nanowire and a second nanowire. Source/drain structures are formed adjacent the channel structure, wherein a liner material is disposed on at least a portion of the sidewalls of the source/drain structures. A nanowire spacer structure is formed between the first and second nanowires, wherein the nanowire spacer comprises an oxidized portion of the liner.

公开(公告)号：US20190189749A1

公开(公告)日：2019-06-20

申请号：US16326890

申请日：2016-09-28

Applicant: INTEL CORPORATION

Inventor： Benjamin Chu-Kung ,  Van Le ,  Seung Hoon Sung ,  Jack Kavalieros ,  Ashish Agrawal ,  Harold Kennel ,  Siddharth Chouksey ,  Anand Murthy ,  Tahir Ghani ,  Glenn Glass ,  Cheng-Ying Huang

IPC: H01L29/10 ,  H01L29/36 ,  H01L29/78

CPC classification number: H01L29/1079 ,  H01L21/26506 ,  H01L29/16 ,  H01L29/165 ,  H01L29/36 ,  H01L29/66 ,  H01L29/7851

Abstract: A subfin leakage problem with respect to the silicon-germanium (SiGe)/shallow trench isolation (STI) interface can be mitigated with a halo implant. A halo implant is used to form a highly resistive layer. For example, a silicon substrate layer 204 is coupled to a SiGe layer, which is coupled to a germanium (Ge) layer. A gate is disposed on the Ge layer. An implant is implanted in the Ge layer that causes the layer to become more resistive. However, an area does not receive the implant due to being protected (or covered) by the gate. The area remains less resistive than the remainder of the Ge layer. In some embodiments, the resistive area of a Ge layer can be etched and/or an undercuttage (etch undercut or EUC) can be performed to expose the unimplanted Ge area of the Ge layer.

公开(公告)号：US20180261696A1

公开(公告)日：2018-09-13

申请号：US15779485

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： Glenn Glass ,  Karthik Jambunathan ,  Anand Murthy ,  Chandra Mohapatra ,  Seiyon Kim

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66

Abstract: Methods of forming germanium channel structure are described. An embodiment includes forming a germanium fin on a substrate, wherein a portion of the germanium fin comprises a germanium channel region, forming a gate material on the germanium channel region, and forming a graded source/drain structure adjacent the germanium channel region. The graded source/drain structure comprises a germanium concentration that is higher adjacent the germanium channel region than at a source/drain contact region.

公开(公告)号：US20240321892A1

公开(公告)日：2024-09-26

申请号：US18125880

申请日：2023-03-24

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Glenn Glass ,  Jessica Panella ,  Dan S. Lavric ,  Charles H. Wallace

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: Techniques to form semiconductor devices having one or more epitaxial source or drain regions formed between dielectric walls that separate each adjacent pair of source or drain regions. In an example, a semiconductor device includes a semiconductor region extending in a first direction from a source or drain region. Dielectric walls extend in the first direction adjacent to opposite sides of the source or drain region. The first and second dielectric walls also extend in the first direction through a gate structure present over the semiconductor region. A dielectric liner exists between at least a portion of the first side of the source or drain region and the first dielectric wall and/or at least a portion of the second side of the source or drain region and the second dielectric wall. The dielectric walls may separate the source or drain region from other adjacent source or drain regions.

公开(公告)号：US20220199402A1

公开(公告)日：2022-06-23

申请号：US17133079

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Koustav Ganguly ,  Ryan Keech ,  Harold Kennel ,  Willy Rachmady ,  Ashish Agrawal ,  Glenn Glass ,  Anand Murthy ,  Jack Kavalieros

IPC: H01L21/02 ,  H01L29/16 ,  H01L27/092 ,  H01L29/78

Abstract: High-purity Ge channeled N-type transistors include a Si-based barrier material separating the channel from a Ge source and drain that is heavily doped with an N-type impurity. The barrier material may have nanometer thickness and may also be doped with N-type impurities. Because of the Si content, N-type impurities have lower diffusivity within the barrier material and can be prevented from entering high-purity Ge channel material. In addition to Si, a barrier material may also include C. With the barrier material, an N-type transistor may display higher channel mobility and reduced short-channel effects.

公开(公告)号：US20220059699A1

公开(公告)日：2022-02-24

申请号：US17499605

申请日：2021-10-12

Applicant: Intel Corporation

Inventor： Michael Jackson ,  Anand Murthy ,  Glenn Glass ,  Saurabh Morarka ,  Chandra Mohapatra

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L29/32

Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.