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公开(公告)号：US20160301548A1
公开(公告)日：2016-10-13
申请号：US15187382
申请日：2016-06-20
Applicant: Intel Corporation
Inventor： Tawfiq Musah , Gokce Keskin , Ganesh Balamurugan , James E. Jaussi , Bryan K. Casper
CPC classification number: H04L25/03057 , H04L7/0058 , H04L7/0087 , H04L7/033 , H04L25/03146 , H04L25/14
Abstract: Some embodiments include apparatus and methods having an input to receive an input signal, additional inputs to receive clock signals having different phases to sample the input signal, and a decision feedback equalizer (DFE) having DFE slices. The DFE slices include a number of data comparators to provide data information based on the sampling of the input signal, and a number of phase error comparators to provide phase error information associated with the sampling of the input signal. The number of phase error comparators of the DFE slices is not greater than the number of data comparators of the DFE slices.
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公开(公告)号：US20150161005A1
公开(公告)日：2015-06-11
申请号：US14622776
申请日：2015-02-13
Applicant: Intel Corporation
Inventor： Bryan K. Casper , Stephen R. Mooney , David Dunning , Mozhgan Mansuri , James E. Jaussi
CPC classification number: G06F11/1076 , G11C5/02 , G11C29/12 , H01L2224/16145 , H03M13/15 , H03M13/152
Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.
Abstract translation: 本发明的实施例一般涉及用于混合存储器的系统，方法和装置。 在一个实施例中，混合存储器可以包括封装衬底。 混合存储器还可以包括附接到封装衬底的第一侧的混合存储器缓冲芯片。 高速输入/输出（HSIO）逻辑支持与处理器的HSIO接口。 混合存储器还包括在HSIO接口上支持分组处理协议的分组处理逻辑。 此外，混合存储器还具有垂直堆叠在混合存储器缓冲器上的一个或多个存储器片。
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公开(公告)号：US20250105053A1
公开(公告)日：2025-03-27
申请号：US18473711
申请日：2023-09-25
Applicant: Intel Corporation
Inventor： Adel Elsherbini , Han Wui Then , Feras Eid , James E. Jaussi , Ganesh Balamurugan , Thomas L. Sounart , Johanna Swan , Henning Braunisch , Tushar Kanti Talukdar , Shawna M. Liff
IPC: H01L21/762 , G02B6/30 , G02B6/43 , H01L21/67 , H01L21/683 , H01L21/768
Abstract: Methods of selectively transferring integrated circuit (IC) components between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of IC components over the release layer is received, and a second substrate with one or more adhesive areas is received. The layer of IC components may include one or more waveguides, ring resonators, drivers, photodetectors, transimpedance amplifiers, and/or electronic integrated circuits. The first substrate is partially bonded to the second substrate, such that a subset of IC components on the first substrate are bonded to the adhesive areas on the second substrate. The first substrate is then separated from the second substrate, and the subset of IC components bonded to the second substrate are separated from the first substrate and remain on the second substrate.
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公开(公告)号：US10956268B2
公开(公告)日：2021-03-23
申请号：US16529716
申请日：2019-08-01
Applicant: Intel Corporation
Inventor： Bryan K. Casper , Stephen R. Mooney , David Dunning , Mozhgan Mansuri , James E. Jaussi
Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.
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公开(公告)号：US20200233746A1
公开(公告)日：2020-07-23
申请号：US16844925
申请日：2020-04-09
Applicant: Intel Corporation
Inventor： Bryan K. CASPER , Stephen R. Mooney , David Dunning , Mozhgan Mansuri , James E. Jaussi
Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.
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Patent Agency Ranking
公开(公告)号：US20190354437A1
公开(公告)日：2019-11-21
申请号：US16529716
申请日：2019-08-01
Applicant: Intel Corporation
Inventor： Bryan K. CASPER , Stephen R. Mooney , David Dunning , Mozhgan Mansuri , James E. Jaussi
Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.
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17.发明授权公开(公告)号：US09455529B2
公开(公告)日：2016-09-27
申请号：US14286445
申请日：2014-05-23
Applicant: Intel Corporation
Inventor： Shreyas Sen , Chintan S. Thakkar , James E. Jaussi , Bryan K. Casper
IPC: H01R12/00 , H01R13/6461 , H01R43/20 , H01R13/6586 , H01R13/6598 , H01R13/652 , H01R13/627 , G06F3/044 , H01R13/6464 , H01R13/62 , H01R13/66
CPC classification number: H01R13/6461 , G06F3/044 , G06F2203/04108 , H01R13/6205 , H01R13/627 , H01R13/6464 , H01R13/652 , H01R13/6586 , H01R13/6598 , H01R13/6625 , H01R43/20 , Y10T29/435
Abstract: Techniques for forming high-bandwidth proximity connection between capacitively coupled plug and receptacle are described herein. A system for achieving capacitive coupling between contactless pads is described. The techniques include aligning and retaining the plug and receptacle in close proximity to one another. The techniques include cancelling crosstalk in the system based on the symmetry and orientation of differential pairs comprising signal pads. The techniques include enabling a high-bandwidth proximity transmission by filtering the transmission using a silicon buffer component.
Abstract translation: 本文描述了用于在电容耦合插头和插座之间形成高带宽接近连接的技术。 描述了用于实现非接触焊盘之间的电容耦合的系统。 这些技术包括将插头和插座对准并保持彼此靠近。 这些技术包括基于包括信号焊盘的差分对的对称性和取向来消除系统中的串扰。 这些技术包括通过使用硅缓冲器组件对传输进行滤波来实现高带宽接近传输。
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18.发明授权公开(公告)号：US09223735B2
公开(公告)日：2015-12-29
申请号：US14557699
申请日：2014-12-02
Applicant: INTEL CORPORATION
Inventor： David J. Harriman , Mahesh Wagh , Robert E. Gough , James E. Jaussi
CPC classification number: G06F13/4027 , G06F1/3203 , G06F13/20 , G06F13/4295 , G06N99/005 , Y02D10/14 , Y02D10/151
Abstract: In an embodiment, the present invention includes a protocol stack having a transaction layer and a link layer. In addition a first physical (PHY) unit is coupled to the protocol stack to provide communication between a processor and a device coupled to the processor via a physical link, where the first PHY unit is of a low power communication protocol and includes a first physical unit circuit. In turn, a second PHY unit is coupled to the protocol stack to provide communication between the processor and the device via a sideband channel coupled between the multicore processor and the device separate from the physical link, where the second PHY unit includes a second physical unit circuit. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括具有事务层和链路层的协议栈。 另外，第一物理（PHY）单元被耦合到协议栈，以经由物理链路提供处理器和耦合到处理器的设备之间的通信，其中第一PHY单元是低功率通信协议，并且包括第一物理 单位电路。 反过来，第二PHY单元被耦合到协议栈，以经由耦合在与物理链路分离的多核处理器和设备之间的边带信道来提供处理器和设备之间的通信，其中第二PHY单元包括第二物理单元 电路。 描述和要求保护其他实施例。
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公开(公告)号：US11664568B2
公开(公告)日：2023-05-30
申请号：US16437245
申请日：2019-06-11
Applicant: Intel Corporation
Inventor： Cooper S. Levy , Chintan S. Thakkar , James E. Jaussi , Bryan K. Casper
Abstract: Embodiments disclosed herein include waveguides. In an embodiment, a waveguide comprises a conductive shell and a first ridge within the conductive shell. In an embodiment, the first ridge extends away from the conductive shell. In an embodiment, the waveguide further comprises a first core over the first ridge, where the first core comprises a first dielectric material with a first permittivity. In an embodiment, the waveguide may further comprise a second core embedded in the first core, where the second core comprises a second dielectric material with a second permittivity that is greater than the first permittivity.
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公开(公告)号：US09929775B2
公开(公告)日：2018-03-27
申请号：US14668199
申请日：2015-03-25
Applicant: Intel Corporation
Inventor： Shreyas Sen , Chintan S. Thakkar , Bryan K. Casper , James E. Jaussi
CPC classification number: H04B5/0012 , H01P3/16 , H01Q13/24 , H04B5/0031
Abstract: Embodiments of the present disclosure provide apparatuses and systems for proximity communications. The apparatus may include an integrated circuit (IC) package with a central processing unit (CPU) circuit, an input-output (I/O) circuit coupled with the CPU circuit, and a dielectric electromagnetic waveguide coupled with the I/O circuit, to enable communications between the CPU circuit and another apparatus. In another instance, the apparatus may include a plurality of coupler pads disposed on a first surface of the apparatus; and a processor electrically coupled with the coupler pads. One of the coupler pads may form capacitive coupling with one of coupler pads disposed on a second surface of another apparatus, in response to a placement of the first surface in at least partial contact with the second surface, to enable proximity data communication between the processor and the other apparatus. Other embodiments may be described and/or claimed.
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