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    Systems, methods, and apparatuses for stacked memory
    1.
    发明授权
    Systems, methods, and apparatuses for stacked memory 有权

    公开(公告)号：US11003534B2

    公开(公告)日：2021-05-11

    申请号：US16844925

    申请日：2020-04-09

    Applicant: Intel Corporation

    Inventor： Bryan K. Casper ,  Stephen R. Mooney ,  David Dunning ,  Mozhgan Mansuri ,  James E. Jaussi

    IPC: G06F11/10 ,  H03M13/15 ,  G11C29/12 ,  G11C5/02

    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

    M-ARY PULSE AMPLITUDE MODULATION DIGITAL EQUALIZER
    3.
    发明申请
    M-ARY PULSE AMPLITUDE MODULATION DIGITAL EQUALIZER 审中-公开

    公开(公告)号：US20170180002A1

    公开(公告)日：2017-06-22

    申请号：US14973163

    申请日：2015-12-17

    Applicant: Intel Corporation

    Inventor： Shiva Kiran ,  Tzu-Chien Hsueh ,  James E. Jaussi

    IPC: H04B3/14 ,  H04B14/02 ,  H04B1/00

    CPC classification number: H04B3/145 ,  H04B1/0007 ,  H04B14/023

    Abstract: Some embodiments include apparatus and methods using an input node, an analog to digital converter (ADC) including an input coupled to the input node, a first feedforward equalizer (FFE) including an input coupled to an output of the ADC, a second FFE including an input coupled to the output of the ADC, and a decision feedback equalizer (DFE) including a first input, a second input, and an output, the first input coupled to an output of the first FFE, and the second input coupled to an output of the second FFE.

    Providing a consolidated sideband communication channel between devices
    4.
    发明授权
    Providing a consolidated sideband communication channel between devices 有权
    在设备之间提供整合的边带通信通道

    公开(公告)号：US08924620B2

    公开(公告)日：2014-12-30

    申请号：US14011009

    申请日：2013-08-27

    Applicant: Intel Corporation

    Inventor： David J. Harriman ,  Mahesh Wagh ,  Robert E. Gough ,  James E. Jaussi

    IPC: G06F13/20 ,  G06F13/40

    CPC classification number: G06F13/4027 ,  G06F1/3203 ,  G06F13/20 ,  G06F13/4295 ,  G06N99/005 ,  Y02D10/14 ,  Y02D10/151

    Abstract: In an embodiment, the present invention includes a protocol stack having a transaction layer and a link layer. In addition a first physical (PHY) unit is coupled to the protocol stack to provide communication between a processor and a device coupled to the processor via a physical link, where the first PHY unit is of a low power communication protocol and includes a first physical unit circuit. In turn, a second PHY unit is coupled to the protocol stack to provide communication between the processor and the device via a sideband channel coupled between the multicore processor and the device separate from the physical link, where the second PHY unit includes a second physical unit circuit. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括具有事务层和链路层的协议栈。 另外，第一物理（PHY）单元被耦合到协议栈，以经由物理链路提供处理器和耦合到处理器的设备之间的通信，其中第一PHY单元是低功率通信协议，并且包括第一物理 单位电路。 反过来，第二PHY单元被耦合到协议栈，以经由耦合在与物理链路分离的多核处理器和设备之间的边带信道来提供处理器和设备之间的通信，其中第二PHY单元包括第二物理单元 电路。 描述和要求保护其他实施例。

    M-ary pulse amplitude modulation digital equalizer
    6.
    发明授权
    M-ary pulse amplitude modulation digital equalizer 有权

    公开(公告)号：US10263663B2

    公开(公告)日：2019-04-16

    申请号：US14973163

    申请日：2015-12-17

    Applicant: Intel Corporation

    Inventor： Shiva Kiran ,  Tzu-Chien Hsueh ,  James E. Jaussi

    IPC: H04B1/00 ,  H04B3/14 ,  H04B14/02

    Abstract: Some embodiments include apparatus and methods using an input node, an analog to digital converter (ADC) including an input coupled to the input node, a first feedforward equalizer (FFE) including an input coupled to an output of the ADC, a second FFE including an input coupled to the output of the ADC, and a decision feedback equalizer (DFE) including a first input, a second input, and an output, the first input coupled to an output of the first FFE, and the second input coupled to an output of the second FFE.

    TECHNIQUES FOR DEVICE-TO-DEVICE COMMUNICATIONS
    7.
    发明申请
    TECHNIQUES FOR DEVICE-TO-DEVICE COMMUNICATIONS 有权
    用于设备到设备通信的技术

    公开(公告)号：US20160285513A1

    公开(公告)日：2016-09-29

    申请号：US14668199

    申请日：2015-03-25

    Applicant: Intel Corporation

    Inventor： Shreyas Sen ,  Chintan S. Thakkar ,  Bryan K. Casper ,  James E. Jaussi

    IPC: H04B5/00 ,  H04W76/04 ,  H01P3/16

    CPC classification number: H04B5/0012 ,  H01P3/16 ,  H01Q13/24 ,  H04B5/0031

    Abstract: Embodiments of the present disclosure provide apparatuses and systems for proximity communications. The apparatus may include an integrated circuit (IC) package with a central processing unit (CPU) circuit, an input-output (I/O) circuit coupled with the CPU circuit, and a dielectric electromagnetic waveguide coupled with the I/O circuit, to enable communications between the CPU circuit and another apparatus. In another instance, the apparatus may include a plurality of coupler pads disposed on a first surface of the apparatus; and a processor electrically coupled with the coupler pads. One of the coupler pads may form capacitive coupling with one of coupler pads disposed on a second surface of another apparatus, in response to a placement of the first surface in at least partial contact with the second surface, to enable proximity data communication between the processor and the other apparatus. Other embodiments may be described and/or claimed.

    Abstract translation: 本公开的实施例提供用于邻近通信的装置和系统。 该装置可以包括具有中央处理单元（CPU）电路，与CPU电路耦合的输入输出（I / O）电路和与I / O电路耦合的介电电磁波导的集成电路（IC）封装， 以实现CPU电路和另一装置之间的通信。 在另一种情况下，该设备可以包括设置在设备的第一表面上的多个耦合器焊盘; 以及与耦合器焊盘电耦合的处理器。 响应于第一表面与第二表面至少部分接触的布置，耦合器中的一个可以与设置在另一装置的第二表面上的耦合器焊盘之一形成电容耦合，以使处理器之间的接近数据通信 和另一台设备。 可以描述和/或要求保护其他实施例。

    WIRELINE RECEIVER CIRCUITRY HAVING COLLABORATIVE TIMING RECOVERY
    8.
    发明申请
    WIRELINE RECEIVER CIRCUITRY HAVING COLLABORATIVE TIMING RECOVERY 有权
    具有协调时序恢复的线路接收器电路

    公开(公告)号：US20160182259A1

    公开(公告)日：2016-06-23

    申请号：US14573343

    申请日：2014-12-17

    Applicant: Intel Corporation

    Inventor： Tawfiq Musah ,  Gokce Keskin ,  Ganesh Balamurugan ,  James E. Jaussi ,  Bryan K. Casper

    IPC: H04L25/03 ,  H04L7/02

    CPC classification number: H04L25/03057 ,  H04L7/0058 ,  H04L7/0087 ,  H04L7/033 ,  H04L25/03146 ,  H04L25/14

    Abstract: Some embodiments include apparatus and methods having an input to receive an input signal, additional inputs to receive clock signals having different phases to sample the input signal, and a decision feedback equalizer (DFE) having DFE slices. The DFE slices include a number of data comparators to provide data information based on the sampling of the input signal, and a number of phase error comparators to provide phase error information associated with the sampling of the input signal. The number of phase error comparators of the DFE slices is not greater than the number of data comparators of the DFE slices.

    Abstract translation: 一些实施例包括具有用于接收输入信号的输入的装置和方法，用于接收具有不同相位以对输入信号进行采样的时钟信号的附加输入以及具有DFE切片的判决反馈均衡器（DFE）。 DFE片包括多个数据比较器，用于基于输入信号的采样来提供数据信息，以及多个相位误差比较器，以提供与输入信号的采样相关联的相位误差信息。 DFE切片的相位误差比较器的数量不大于DFE切片的数据比较器的数量。

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