公开(公告)号：US20180197966A1

公开(公告)日：2018-07-12

申请号：US15743847

申请日：2015-07-17

Applicant: Intel Corporation

Inventor： Chen-Guan Lee ,  Joodong Park ,  En-Shao Liu ,  Everett S. Cassidy-Comfort ,  Walid M. Hafez ,  Chia-Hong Jan

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L21/764 ,  H01L21/768

CPC classification number: H01L29/4991 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/78

Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.

公开(公告)号：US09520494B2

公开(公告)日：2016-12-13

申请号：US14913326

申请日：2013-09-26

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid M. Hafez ,  Curtis Tsai ,  Jeng-Ya D. Yeh ,  Joodong Park

IPC: H01L29/772 ,  H01L29/78 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L27/12 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78642

Abstract: Vertical non-planar semiconductor devices for system-on-chip (SoC) applications and methods of fabricating vertical non-planar semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate, the semiconductor fin having a recessed portion and an uppermost portion. A source region is disposed in the recessed portion of the semiconductor fin. A drain region is disposed in the uppermost portion of the semiconductor fin. A gate electrode is disposed over the uppermost portion of the semiconductor fin, between the source and drain regions.

Abstract translation: 描述了用于片上系统（SoC）应用的垂直非平面半导体器件和制造垂直非平面半导体器件的方法。 例如，半导体器件包括设置在衬底上方的半导体鳍片，半导体鳍片具有凹部和最上部。 源极区域设置在半导体鳍片的凹部中。 漏极区域设置在半导体鳍片的最上部。 栅电极设置在半导体鳍片的最上部分之间，在源区和漏区之间。

公开(公告)号：US11824002B2

公开(公告)日：2023-11-21

申请号：US16457712

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： En-Shao Liu ,  Joodong Park ,  Chen-Guan Lee ,  Walid M. Hafez ,  Chia-Hong Jan ,  Jiansheng Xu

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53209

Abstract: An integrated circuit structure comprises a base and a plurality of metal levels over the base. A first metal level includes a first dielectric material. The first metal level further includes a first plurality of interconnect lines in the first dielectric material, wherein the first plurality of interconnect lines in the first metal level have variable widths from relatively narrow to relatively wide, and wherein the first plurality of interconnect lines have variable heights based on the variable widths, such that a relatively wide one of the first plurality of interconnect lines has a taller height from the substrate than a relatively narrow one of the first plurality of interconnect lines, and a shorter distance to a top of the first metal level.

公开(公告)号：US11610917B2

公开(公告)日：2023-03-21

申请号：US17568652

申请日：2022-01-04

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Jeng-Ya D. Yeh ,  Curtis Tsai ,  Joodong Park ,  Chia-Hong Jan ,  Gopinath Bhimarasetti

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

公开(公告)号：US10923574B2

公开(公告)日：2021-02-16

申请号：US16569879

申请日：2019-09-13

Applicant: INTEL CORPORATION

Inventor： En-Shao Liu ,  Joodong Park ,  Chen-Guan Lee ,  Jui-Yen Lin ,  Chia-Hong Jan

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  B82Y10/00 ,  H01L29/775 ,  H01L21/3213 ,  H01L21/764 ,  H01L29/78 ,  H01L29/51 ,  H01L29/786 ,  H01L29/06 ,  H01L29/08

Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, C-shape, -shape, ⊥-shape, L-shape, or ┘-shape, for example.

公开(公告)号：US10204999B2

公开(公告)日：2019-02-12

申请号：US15743847

申请日：2015-07-17

Applicant: Intel Corporation

Inventor： Chen-Guan Lee ,  Joodong Park ,  En-Shao Liu ,  Everett S. Cassidy-Comfort ,  Walid M. Hafez ,  Chia-Hong Jan

IPC: H01L29/49 ,  H01L21/764 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768

Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.

公开(公告)号：US09780217B2

公开(公告)日：2017-10-03

申请号：US14780218

申请日：2013-06-26

Applicant: Intel Corporation

Inventor： Jeng-Ya D. Yeh ,  Chia-Hong Jan ,  Walid M. Hafez ,  Joodong Park

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7851 ,  H01L29/42368 ,  H01L29/66795 ,  H01L29/785

Abstract: Non-planar semiconductor devices having self-aligned fins with top blocking layers and methods of fabricating non-planar semiconductor devices having self-aligned fins with top blocking layers are described. For example, a semiconductor structure includes a semiconductor fin disposed above a semiconductor substrate and having a top surface. An isolation layer is disposed on either side of the semiconductor fin, and recessed below the top surface of the semiconductor fin to provide a protruding portion of the semiconductor fin. The protruding portion has sidewalls and the top surface. A gate blocking layer has a first portion disposed on at least a portion of the top surface of the semiconductor fin, and has a second portion disposed on at least a portion of the sidewalls of the semiconductor fin. The first portion of the gate blocking layer is continuous with, but thicker than, the second portion of the gate blocking layer. A gate stack is disposed on the first and second portions of the gate blocking layer.

公开(公告)号：US09741721B2

公开(公告)日：2017-08-22

申请号：US14912890

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Joodong Park ,  Gopinath Bhimarasetti ,  Rahul Ramaswamy ,  Chia-Hong Jan ,  Walid M. Hafez ,  Jeng-Ya D. Yeh ,  Curtis Tsai

IPC: H01L27/108 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/10826 ,  H01L27/10808 ,  H01L27/10879 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7854

Abstract: Low leakage non-planar access transistors for embedded dynamic random access memory (eDRAM) and methods of fabricating low leakage non-planar access transistors for eDRAM are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate and including a narrow fin region disposed between two wide fin regions. A gate electrode stack is disposed conformal with the narrow fin region of the semiconductor fin, the gate electrode stack including a gate electrode disposed on a gate dielectric layer. The gate dielectric layer includes a lower layer and an upper layer, the lower layer composed of an oxide of the semiconductor fin. A pair of source/drain regions is included, each of the source/drain regions disposed in a corresponding one of the wide fin regions.

公开(公告)号：US20170069758A1

公开(公告)日：2017-03-09

申请号：US15353631

申请日：2016-11-16

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid M. Hafez ,  Curtis Tsai ,  Jeng-Ya D. Yeh ,  Joodong Park

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L27/12 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78642

Abstract: Vertical non-planar semiconductor devices for system-on-chip (SoC) applications and methods of fabricating vertical non-planar semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate, the semiconductor fin having a recessed portion and an uppermost portion. A source region is disposed in the recessed portion of the semiconductor fin. A drain region is disposed in the uppermost portion of the semiconductor fin. A gate electrode is disposed over the uppermost portion of the semiconductor fin, between the source and drain regions.

Abstract translation: 描述了用于片上系统（SoC）应用的垂直非平面半导体器件和制造垂直非平面半导体器件的方法。 例如，半导体器件包括设置在衬底上方的半导体鳍片，半导体鳍片具有凹部和最上部。 源极区域设置在半导体鳍片的凹部中。 漏极区域设置在半导体鳍片的最上部。 栅电极设置在半导体鳍片的最上部分之间，在源区和漏区之间。

公开(公告)号：US11881486B2

公开(公告)日：2024-01-23

申请号：US18111313

申请日：2023-02-17

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Jeng-Ya D. Yeh ,  Curtis Tsai ,  Joodong Park ,  Chia-Hong Jan ,  Gopinath Bhimarasetti

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L27/1211 ,  H01L21/0228 ,  H01L21/02164 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/28158 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/845 ,  H01L29/42356 ,  H01L29/51 ,  H01L29/513 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66545

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.