公开(公告)号：US10249597B2

公开(公告)日：2019-04-02

申请号：US15283055

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Kalyan C. Kolluru ,  Pete D. Vogt ,  Christopher J. Nelson ,  Amande B. Trang ,  Uddalak Bhattacharya

IPC: G11C5/06 ,  H01L25/065 ,  H01L25/18 ,  G11C5/02 ,  G11C29/02 ,  G11C29/12 ,  G11C29/48 ,  G11C29/00

Abstract: Systems, methods, and apparatuses for implementing die recovery in Two-Level Memory (2LM) stacked die subsystems are described. A stacked semiconductor package includes a processor functional silicon die at a first layer of the stacked semiconductor package; one or more memory dies forming a corresponding one or more memory layers of the stacked semiconductor package; a plurality of Through Silicon Vias (TSV s) formed through the one or more memory dies; a plurality of physical memory interfaces electrically interfacing the one or more memory dies to the processor functional silicon die at the first layer through the memory layers via the plurality of TSVs; and a redundant physical memory interface formed by a redundant TSV traversing through the memory layers to the processor functional silicon die at the first layer through which to reroute a memory signal path from a defective physical memory interface at a defective TSV to a functional signal path traversing the redundant TSV.

公开(公告)号：US20240170581A1

公开(公告)日：2024-05-23

申请号：US17992057

申请日：2022-11-22

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Ayan Kar ,  Patrick Morrow ,  Charles C. Kuo ,  Nicholas A. Thomson ,  Benjamin Orr ,  Kalyan C. Kolluru ,  Marko Radosavljevic ,  Jack T. Kavalieros

IPC: H01L29/861 ,  H01L27/02 ,  H01L27/06 ,  H01L29/06

CPC classification number: H01L29/8611 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/0649

Abstract: An integrated circuit structure includes a sub-fin having at least a first portion that is doped with a first type of dopant, and a second portion that is doped with a second type of dopant. A PN junction is between the first and second portions of the sub-fin. The first type of dopant is one of a p-type or an n-type dopant, and the second type of dopant is the other of the p-type or the n-type dopant. A first contact and a second contact comprise conductive material. In an example, the first contact and the second contact are respectively in contact with the first portion and the second portion of the sub-fin. A diode is formed based on the PN junction between the first and second portions, where the first contact is an anode contact of the diode, and the second contact is a cathode contact of the diode.

公开(公告)号：US20240088134A1

公开(公告)日：2024-03-14

申请号：US17943815

申请日：2022-09-13

Applicant: Intel Corporation

Inventor： Nicholas A. Thomson ,  Ayan Kar ,  Kalyan C. Kolluru ,  Mauro J. Kobrinsky

IPC: H01L27/02 ,  H01L21/8234

CPC classification number: H01L27/0266 ,  H01L21/823418 ,  H01L21/823481

Abstract: An integrated circuit structure includes laterally adjacent first and second devices. The first device has (i) a first diffusion region, (ii) a first body including semiconductor material extending laterally from the first diffusion region, and (iii) a first gate structure on the first body. The first diffusion region has a first lower section that extends below a lower surface of the first gate structure, the first lower section having a first height. The second device has (i) a second diffusion region, (ii) a second body including semiconductor material extending laterally from the second diffusion region, and (iii) a second gate structure on the second body. The second diffusion region has a second lower section that extends below a lower surface of the second gate structure, the second lower section having a second height. In an example, the first height is at least 2 nanometers greater than the second height.

公开(公告)号：US20240088133A1

公开(公告)日：2024-03-14

申请号：US17943840

申请日：2022-09-13

Applicant: INTEL CORPORATION

Inventor： Nicholas A. Thomson ,  Ayan Kar ,  Kalyan C. Kolluru ,  Mauro J. Kobrinksy ,  Benjamin Orr

IPC: H01L27/02 ,  H01L23/528 ,  H01L29/06 ,  H01L29/861

CPC classification number: H01L27/0255 ,  H01L23/5283 ,  H01L27/0266 ,  H01L29/0673 ,  H01L29/8611

Abstract: An integrated circuit structure includes a sub-fin having a first type of dopant, a first diffusion region having the first type of dopant and in contact with the sub-fin, and a second diffusion region and a third diffusion region having a second type of dopant and in contact with the sub-fin. The first type of dopant is one of p-type or n-type dopant, and where the second type of dopant is the other of the p-type or n-type dopant. A first body of semiconductor material extends from the second diffusion region to the third diffusion region, and a second body of semiconductor material extends from the first diffusion region towards the second diffusion region. The first diffusion region is a tap diffusion region contacting the sub-fin. In an example, the first diffusion region facilitates formation of a diode for electrostatic discharge (ESD) protection of the integrated circuit structure.

公开(公告)号：US20240088132A1

公开(公告)日：2024-03-14

申请号：US17943819

申请日：2022-09-13

Applicant: Intel Corporation

Inventor： Nicholas A. Thomson ,  Kalyan C. Kolluru ,  Ayan Kar ,  Chu-Hsin Liang ,  Benjamin Orr ,  Biswajeet Guha ,  Brian Greene ,  Chung-Hsun Lin ,  Sabih U. Omar ,  Sameer Jayanta Joglekar

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/861

CPC classification number: H01L27/0255 ,  H01L29/0673 ,  H01L29/8611

Abstract: An integrated circuit structure includes a sub-fin having (i) a first portion including a p-type dopant and (ii) a second portion including an n-type dopant. A first body of semiconductor material is above the first portion of the sub-fin, and a second body of semiconductor material is above the second portion of the sub-fin. In an example, the first portion of the sub-fin and the second portion of the sub-fin are in contact with each other, to form a PN junction of a diode. For example, the first portion of the sub-fin is part of an anode of the diode, and wherein the second portion of the sub-fin is part of a cathode of the diode.

公开(公告)号：US20240088131A1

公开(公告)日：2024-03-14

申请号：US17943812

申请日：2022-09-13

Applicant: Intel Corporation

Inventor： Nicholas A. Thomson ,  Kalyan C. Kolluru ,  Ayan Kar ,  Mauro J. Kobrinsky

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/861

CPC classification number: H01L27/0255 ,  H01L27/0266 ,  H01L29/0673 ,  H01L29/8611

Abstract: An integrated circuit structure includes a sub-fin having at least a portion that is doped with a first type of dopant, and a diffusion region doped with a second type of dopant. The diffusion region is in contact with the sub-fin and extends upward from the sub-fin. The first type of dopant is one of a p-type or an n-type dopant, and the second type of dopant is the other of the p-type or the n-type dopant. In an example, a first conductive contact is above and on the diffusion region, and a second conductive contact is in contact with the portion of the sub-fin. In an example, the diffusion region is at least a part of one of an anode or a cathode of a diode, and the portion of the sub-fin is at least a part of the other of the anode or the cathode of the diode.

公开(公告)号：US11791331B2

公开(公告)日：2023-10-17

申请号：US17526199

申请日：2021-11-15

Applicant: Intel Corporation

Inventor： Nicholas A. Thomson ,  Kalyan C. Kolluru ,  Adam Clay Faust ,  Frank Patrick O'Mahony ,  Ayan Kar ,  Rui Ma

IPC: H01L27/02

CPC classification number: H01L27/0292 ,  H01L27/0255 ,  H01L27/0288

Abstract: Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway.

公开(公告)号：US20230088578A1

公开(公告)日：2023-03-23

申请号：US17448385

申请日：2021-09-22

Applicant: INTEL CORPORATION

Inventor： Nicholas A. Thomson ,  Ayan Kar ,  Benjamin Orr ,  Kalyan C. Kolluru ,  Nathan D. Jack ,  Patrick Morrow ,  Cheng-Ying Huang ,  Charles C. Kuo

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8238

Abstract: Integrated circuits including lateral diodes. In an example, diodes are formed with laterally neighboring source and drain regions (diffusion regions) configured with different polarity epitaxial growths (e.g., p-type and n-type), to provide an anode and cathode of the diode. In some such cases, dopants may be used in the channel region to create or otherwise enhance a PN or PIN junction between the diffusion regions and the semiconductor material of a channel region. The channel region can be, for instance, one or more nanoribbons or other such semiconductor bodies that extend between the oppositely-doped diffusion regions. In some cases, nanoribbons making up the channel region are left unreleased, thereby preserving greater volume through which diode current can flow. Other features include skipped epitaxial regions, elongated gate structures, using isolation structures in place of gate structures, and/or sub-fin conduction paths that are supplemental or alternative to a channel-based conduction paths.

公开(公告)号：US20230087444A1

公开(公告)日：2023-03-23

申请号：US17448384

申请日：2021-09-22

Applicant: INTEL CORPORATION

Inventor： Nicholas A. Thomson ,  Ayan Kar ,  Benjamin Orr ,  Kalyan C. Kolluru ,  Nathan D. Jack ,  Patrick Morrow ,  Cheng-Ying Huang ,  Charles C. Kuo

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8238

Abstract: Integrated circuits including lateral diodes. In an example, diodes are formed with laterally neighboring source and drain regions (diffusion regions) configured with different polarity epitaxial growths (e.g., p-type and n-type), to provide an anode and cathode of the diode. In some such cases, dopants may be used in the channel region to create or otherwise enhance a PN or PIN junction between the diffusion regions and the semiconductor material of a channel region. The channel region can be, for instance, one or more nanoribbons or other such semiconductor bodies that extend between the oppositely-doped diffusion regions. In some cases, nanoribbons making up the channel region are left unreleased, thereby preserving greater volume through which diode current can flow. Other features include skipped epitaxial regions, elongated gate structures, using isolation structures in place of gate structures, and/or sub-fin conduction paths that are supplemental or alternative to a channel-based conduction path.

公开(公告)号：US20220399277A1

公开(公告)日：2022-12-15

申请号：US17345969

申请日：2021-06-11

Applicant: INTEL CORPORATION

Inventor： Adel A. Elsherbini ,  Scott E. Siers ,  Sathya Narasimman Tiagaraj ,  Gerald S. Pasdast ,  Zhiguo Qian ,  Kalyan C. Kolluru ,  Vivek Kumar Rajan ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

Abstract: An Integrated Circuit (IC), comprising a first conductive trace on a first die, a second conductive trace on a second die, and a conductive pathway electrically coupling the first conductive trace with the second conductive trace. The second die is coupled to the first die with interconnects. The conductive pathway comprises a portion of the interconnects located proximate to a periphery of a region in the first die through which the first conductive trace is not routable. In some embodiments, the conductive pathway reroutes electrical connections away from the region. The region comprises a high congestion zone having high routing density in some embodiments. In other embodiments, the region comprises a “keep-out” zone.