公开(公告)号：US20170323963A1

公开(公告)日：2017-11-09

申请号：US15528802

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Sanaz K. GARDNER ,  Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Chandra S. MOHAPATRA ,  Anand S. MURTHY ,  Nadia RAHHAL-ORABI ,  Nancy M. ZELICK ,  Tahir GHANI

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/205 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/66818

Abstract: An embodiment includes a device comprising: a fin structure including an upper portion and a lower portion, the upper portion having a bottom surface directly contacting an upper surface of the lower portion; wherein (a) the lower portion is included in a trench having an aspect ratio (depth to width) of at least 2:1; (b) the bottom surface has a bottom maximum width and the upper surface has an upper maximum width that is greater the bottom maximum width; (c) the bottom surface covers a middle portion of the upper surface but does not cover lateral portions of the upper surface; and (d) the upper portion includes an upper III-V material and the lower portion includes a lower III-V material different from the upper III-V material. Other embodiments are described herein.

公开(公告)号：US20170309734A1

公开(公告)日：2017-10-26

申请号：US15626067

申请日：2017-06-16

Applicant: Intel Corporation

Inventor： Suman DATTA ,  Mantu K. HUDAIT ,  Mark L. DOCZY ,  Jack T. KAVALIEROS ,  Amlan MAJUMDAR ,  Justin K. BRASK ,  Been-Yih JIN ,  Matthew V. METZ ,  Robert S. CHAU

IPC: H01L29/778 ,  H01L29/205 ,  H01L27/092 ,  H01L29/15 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/7784 ,  H01L21/02178 ,  H01L21/02381 ,  H01L21/02546 ,  H01L21/823807 ,  H01L21/823885 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/15 ,  H01L29/157 ,  H01L29/205 ,  H01L29/41783 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7783

Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.

公开(公告)号：US20240006484A1

公开(公告)日：2024-01-04

申请号：US17855639

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Ashish Verma PENUMATCHA ,  Kevin P. O'BRIEN ,  Kirby MAXEY ,  Carl H. NAYLOR ,  Chelsey DOROW ,  Uygar E. AVCI ,  Matthew V. METZ ,  Sudarat LEE ,  Chia-Ching LIN ,  Sean T. MA

IPC: H01L29/06 ,  H01L29/778 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/78696 ,  H01L29/42392 ,  H01L29/778

Abstract: Embodiments disclosed herein include transistors and methods of forming transistors. In an embodiment, the transistor comprises a channel with a first end and a second end opposite from the first end, a first spacer around the first end of the channel, a second spacer around the second end of the channel, and a gate stack over the channel, where the gate stack is between the first spacer and the second spacer. In an embodiment, the transistor may further comprise a first extension contacting the first end of the channel; and a second extension contacting the first end of the channel. In an embodiment, the transistor further comprises conductive layers over the first extension and the second extension outside of the first spacer and the second spacer.

公开(公告)号：US20230420510A1

公开(公告)日：2023-12-28

申请号：US17850078

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Carl H. NAYLOR ,  Kirby MAXEY ,  Kevin P. O'BRIEN ,  Chelsey DOROW ,  Sudarat LEE ,  Ashish Verma PENUMATCHA ,  Uygar E. AVCI ,  Matthew V. METZ ,  Scott B. CLENDENNING ,  Jiun-Ruey CHEN ,  Chia-Ching LIN ,  Carly ROGAN

IPC: H01L29/06 ,  H01L29/778 ,  H01L29/786 ,  H01L29/18 ,  H01L21/02

CPC classification number: H01L29/0673 ,  H01L29/778 ,  H01L29/78696 ,  H01L29/18 ,  H01L21/02499 ,  H01L21/02568 ,  H01L21/02485

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to creating a transistor structure by selectively growing a 2D TMD directly in a stacked channel configuration, such as a stacked nanowire or nanoribbon formation. In embodiments, this TMD growth may occur for all of the nanowires or nanoribbons in the transistor structure in one stage. Placement of a SAM on a plurality of dielectric layers within the transistor structure stack facilitates channel deposition and channel geometry in the stacked channel configuration. Other embodiments may be described and/or claimed.

公开(公告)号：US20220199628A1

公开(公告)日：2022-06-23

申请号：US17129869

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Noriyuki SATO ,  Sarah ATANASOV ,  Abhishek A. SHARMA ,  Bernhard SELL ,  Chieh-Jen KU ,  Arnab SEN GUPTA ,  Matthew V. METZ ,  Elliot N. TAN ,  Hui Jae YOO ,  Travis W. LAJOIE ,  Van H. LE ,  Pei-Hua WANG

IPC: H01L27/108 ,  H01L29/786

Abstract: An integrated circuit (IC) structure in a memory device is described. In an example, the IC structure includes a memory cell including a bitline (BL) extending along a first direction and a channel extending along a second direction above and diagonal to the BL. In the example, a wordline (WL) extends in a third direction perpendicular to the first direction of the BL and intersects with the channel to control a current in the channel along a gated channel length. In some examples, the channel is electrically coupled on a first side to a storage capacitor via a storage node contact (SNC) and on a second side to the BL via a bit line contact (BLC) located on an underside or backside of the channel.

公开(公告)号：US20210408239A1

公开(公告)日：2021-12-30

申请号：US16913848

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Siddharth CHOUKSEY ,  Ashish AGRAWAL ,  Seung Hoon SUNG ,  Jack T. KAVALIEROS ,  Matthew V. METZ ,  Willy RACHMADY ,  Jessica TORRES ,  Martin M. MITAN

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/768 ,  H01L27/088

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a stack of semiconductor channels with a first end and second end. In an embodiment, individual ones of the semiconductor channels comprise a nitrided surface. In an embodiment, the semiconductor device further comprises a source region at the first end of the stack and a drain region at the second end of the stack. In an embodiment, a gate dielectric surrounds the semiconductor channels, and a gate electrode surrounding the gate dielectric.

公开(公告)号：US20190296145A1

公开(公告)日：2019-09-26

申请号：US16316337

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Sean T. MA ,  Harold KENNEL

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/417 ,  H01L29/20

Abstract: A buffer layer is deposited on a substrate. A first III-V semiconductor layer is deposited on the buffer layer. A second III-V semiconductor layer is deposited on the first III-V semiconductor layer. The second III-V semiconductor layer comprises a channel portion and a source/drain portion. The first III-V semiconductor layer acts as an etch stop layer to etch a portion of the second III-V semiconductor layer to form the source/drain portion.

公开(公告)号：US20190103486A1

公开(公告)日：2019-04-04

申请号：US16099532

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Van H. LE ,  Matthew V. METZ ,  Benjamin CHU-KUNG ,  Ashish AGRAWAL ,  Jack T. KAVALIEROS

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L23/31 ,  H01L23/29

Abstract: An apparatus including a transistor device including a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel includes a length dimension between source and drain that is greater than a length dimension of the gate electrode such that there is a passivated underlap between an edge of the gate electrode and an edge of the channel relative to each of the source and the drain. A method including forming a channel of a transistor device on a substrate; forming first and second passivation layers on a surface of substrate on opposite sides of the channel; forming a gate stack on the channel between first and second passivation layers; and forming a source on the substrate between the channel and the first passivation layer and a drain on the substrate between the channel and the second passivation layer.

公开(公告)号：US20180315827A1

公开(公告)日：2018-11-01

申请号：US15770468

申请日：2015-12-17

Applicant: Intel Corporation

Inventor： Sean T. MA ,  Willy RACHMADY ,  Matthew V. METZ ,  Chandra S. MOHAPATRA ,  Gilbert DEWEY ,  Nadia M. RAHHAL-ORABI ,  Jack T. KAVALIEROS ,  Anand S. MURTHY

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/205 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/4966 ,  H01L21/28264 ,  H01L29/1054 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: An apparatus including a non-planar body on a substrate, the body including a channel on a blocking material, and a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel material and a second gate electrode material including a second work function different from the first work function disposed on the channel material and on the blocking material. A method including forming a non-planar body on a substrate, the non-planar body including a channel on a blocking material, and forming a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel and a second gate electrode material including a second work function different from the first work function disposed on the channel and on the blocking material.

公开(公告)号：US20180261498A1

公开(公告)日：2018-09-13

申请号：US15779442

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Sanaz K. GARDNER ,  Willy RACHMADY ,  Van H. LE ,  Matthew V. METZ ,  Seiyon KIM ,  Ashish AGRAWAL ,  Jack T. KAVALIEROS

IPC: H01L21/768 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

Abstract: Related fields of the present disclosure are in the field of transistor devices, and in particular, FinFET device structures formed using aspect ratio trapping trench (ART) process techniques. For example, a FinFET device consistent with the present disclosure comprises a first fin structure including a first upper fin portion atop a first lower fin portion and a second fin structure including a second upper fin portion atop a second lower fin portion. The first and second upper fin structures include a Group IV material and the first and second lower fin structures include a Group III-V material.