公开(公告)号：US11960900B2

公开(公告)日：2024-04-16

申请号：US16729321

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： Murugasamy K. Nachimuthu ,  Rajat Agarwal ,  Mohan J. Kumar

IPC: G06F9/44 ,  G06F9/4401 ,  G06F9/445

CPC classification number: G06F9/4403 ,  G06F9/445

Abstract: Technologies for fast boot-up of a compute device with error-correcting code (ECC) memory are disclosed. A basic input/output system (BIOS) of a compute device may assign memory addresses of the ECC memory to different processors on the compute device. The processors may then initialize the ECC memory in parallel by writing to the ECC memory. The processors may write to the ECC memory with direct-store operations that are immediately written to the ECC memory instead of being cached. The BIOS may continue to operation on one processor while the rest of the processors initialize the ECC memory.

公开(公告)号：US20230402077A1

公开(公告)日：2023-12-14

申请号：US18145095

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Sergej Deutsch ,  Christoph Dobraunig ,  Rajat Agarwal ,  David M. Durham ,  Santosh Ghosh ,  Karanvir Grewal ,  Krystian Matusiewicz

IPC: G06F11/10

CPC classification number: G06F11/1044

Abstract: The technology described herein includes a first plurality of bijection diffusion function circuits to diffuse data bits into diffused data bits and store the diffused data bits into a memory; an error correcting code (ECC) generation circuit to generate ECC bits for the data bits; and a second plurality of bijection diffusion function circuits to diffuse the ECC bits into diffused ECC bits and store the diffused ECC bits into the memory.

公开(公告)号：US11567877B2

公开(公告)日：2023-01-31

申请号：US16402734

申请日：2019-05-03

Applicant: Intel Corporation

Inventor： Suresh S. Chittor ,  Rajat Agarwal ,  Wei P. Chen

IPC: G06F12/0893

Abstract: An embodiment of a memory controller device includes technology to control access to a multi-level memory including at least a first level memory and a second level memory, provide direct access to the first level memory based on a system memory address, cache accesses to the second level memory in a second portion of the first level memory, and address a memory space with a total memory capacity which includes a first capacity of the first portion of the first level memory plus a second capacity of the second level memory. Other embodiments are disclosed and claimed.

公开(公告)号：US11019098B2

公开(公告)日：2021-05-25

申请号：US16023941

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Sergej Deutsch ,  David Durham ,  Karanvir Grewal ,  Rajat Agarwal

IPC: H04L29/06 ,  H04L9/14 ,  H04L9/08 ,  G09C1/00 ,  H04L9/00

Abstract: The present disclosure is directed to systems and methods for providing protection against replay attacks on memory, by refreshing or updating encryption keys. The disclosed replay protected computing system may employ encryption refresh of memory so that unauthorized copies of data are usable for a limited amount of time (e.g., 500 milliseconds or less). The replay protected computing system initially encrypts protected data prior to storage in memory. After a predetermined time or after a number of memory accesses have occurred, the replay protected computing system decrypts the data with the existing key and re-encrypts data with a new key. Unauthorized copies of data (such as those made by an adversary system/program) are not refreshed with subsequent new keys. When an adversary program attempts to use the unauthorized copies of data, the unauthorized copies of data are decrypted with the incorrect keys, which renders the decrypted data unintelligible.

公开(公告)号：US11010304B2

公开(公告)日：2021-05-18

申请号：US15865642

申请日：2018-01-09

Applicant: Intel Corporation

Inventor： Uksong Kang ,  Kjersten E. Criss ,  Rajat Agarwal ,  John B. Halbert

IPC: G11C29/00 ,  H04L1/00 ,  G06F12/0879 ,  G06F3/06 ,  G06F12/02 ,  G11C11/16 ,  G11C11/408 ,  G06F11/10 ,  G06F12/0846 ,  G11C7/10 ,  G06F12/0893 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/409 ,  G11C29/42 ,  G06F12/06

Abstract: A method performed by a memory is described. The method includes sensing first bits from a first activated column associated with a first sub-word line structure simultaneously with the sensing of second bits from a second activated column associated with a second sub-word line structure. The method also includes providing the first bits at a same first bit location within different read words of a burst read sequence and providing the second bits at a same second bit location within the different read words of the burst read sequence.

公开(公告)号：US10725861B2

公开(公告)日：2020-07-28

申请号：US16022447

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Anatoli Bolotov ,  Mikhail Grinchuk ,  Rajat Agarwal

IPC: G06F11/10 ,  H03M13/11 ,  G06F3/06 ,  G11C7/24 ,  H03M13/00 ,  G11C29/52 ,  G11C29/04

Abstract: System and techniques for error correction code (ECC) memory security are described herein. A write request that includes data is received. An integrity check value (ICV) is computed for the data. Then, the write request is performed, including writing a representation of the data to a data area in memory and writing the ICV into an ECC area in memory. Here, the data area is addressable by a host and the ECC area corresponds to the data area via hardware of the memory.

公开(公告)号：US10102126B2

公开(公告)日：2018-10-16

申请号：US15192871

申请日：2016-06-24

Applicant: Intel Corporation

Inventor： Raj K. Ramanujan ,  Rajat Agarwal ,  Glenn J. Hinton

IPC: G06F12/08 ,  G06F12/02 ,  G06F12/0811 ,  G06F12/0808 ,  G11C7/10 ,  G06F12/0815 ,  G06F12/0893 ,  G06F12/0806 ,  G06F12/0888 ,  G11C14/00 ,  G11C13/00

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.

公开(公告)号：US20180285267A1

公开(公告)日：2018-10-04

申请号：US15474654

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Ruchira Sasanka ,  Rajat Agarwal

IPC: G06F12/0811 ,  G06F12/1018 ,  G06F12/1027 ,  G06F12/1009

CPC classification number: G06F12/0811 ,  G06F12/1009 ,  G06F12/1018 ,  G06F12/1027 ,  G06F2212/283 ,  G06F2212/65 ,  G06F2212/68

Abstract: A processor includes a processing core to execute a transaction with a memory via a cache and a cache controller, associated with the processor, comprising an index mapper circuit to identify a physical memory address associated with the transaction, wherein the physical memory address comprises a plurality of bits, determine, based on the plurality of bits, a first set of bits encoding a tag value, a second set of bits encoding a page index value, and a third set of bits encoding a line index value, determine, based on the tag value, a bit-placement order for combining the second set of bits and the third set of bits, combine, based on the bit-placement order, the second set of bits and the third set of bits to form an index, and generate, based on the index, a mapping from the physical memory address to a cache line index value identifying a cache line in the cache, wherein the processing core is to access, based on the cache line, a memory location referenced by the physical memory address.

公开(公告)号：US20180137005A1

公开(公告)日：2018-05-17

申请号：US15814336

申请日：2017-11-15

Applicant: Intel Corporation

Inventor： Wei Wu ,  Uksong Kang ,  Hussein Alameer ,  Rajat Agarwal ,  Kjersten E. Criss ,  John B. Halbert

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/108 ,  G11C5/063 ,  G11C7/10 ,  G11C11/40618 ,  G11C11/4093 ,  G11C29/44 ,  G11C29/52 ,  G11C29/835 ,  G11C29/846

Abstract: In a memory system a multichip memory provides data redundancy for error recovery. The multichip memory can be an integrated circuit package with multiple memory dies or memory devices integrated with a common package. The multiple memory dies are coupled in a daisy chain, and can be a vertical stack or in a planar formation. The memory chip or chips at the end of the chain store parity data, and the other devices store data. The multichip memory includes XOR (exclusive OR) logic to compute parity to store in the redundant parity chips.

公开(公告)号：US20170185473A1

公开(公告)日：2017-06-29

申请号：US14757905

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： Debaleena Das ,  Rajat Agarwal ,  Brian S. Morris

IPC: G06F11/07 ,  G06F3/06

CPC classification number: G06F11/0793 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/1064

Abstract: Provided are an apparatus and method to store data from a cache line at locations having errors in a sparing directory. In response to a write operation having write data for locations in one of the cache lines, the write data for a location in the cache line having an error is written to an entry in a sparing directory including an address of the cache line.