公开(公告)号：US10461007B2

公开(公告)日：2019-10-29

申请号：US15773639

申请日：2015-12-22

Applicant: INTEL CORPORATION

Inventor： Rajendra C. Dias ,  Nachiket R. Raravikar

IPC: H01L23/31 ,  H01L23/552 ,  H01L25/065 ,  H01L21/56 ,  H01L21/762 ,  H01L21/02

Abstract: Semiconductor packages with electromagnetic interference (EMI) shielding and a method of manufacture therefor is disclosed. The semiconductor packages may house single electronic components or may be a system in a package (SiP) implementation. The EMI shielding may be provided on top of and along the periphery of the semiconductor package. The EMI shielding on the periphery may be formed of cured conductive ink or cured conductive paste disposed on sidewalls of molding that encapsulates the electronic component(s) provided on the semiconductor package. The top portion of the EMI shielding may be a laminated metal sheet provided on a top surface of the molding. The semiconductor package may further have vertical portions of the EMI shielding with conductive ink filled trenches in the molding that may separate one or more electronic components from other electronic components of the semiconductor package.

公开(公告)号：US20180323128A1

公开(公告)日：2018-11-08

申请号：US15773639

申请日：2015-12-22

Applicant: INTEL CORPORATION

Inventor： Rajendra C. Dias ,  Nachiket R. Raravikar

IPC: H01L23/31 ,  H01L23/552 ,  H01L25/065 ,  H01L21/56 ,  H01L21/762

CPC classification number: H01L23/3128 ,  H01L21/02098 ,  H01L21/561 ,  H01L21/565 ,  H01L21/762 ,  H01L23/552 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/73204

Abstract: Semiconductor packages with electromagnetic interference (EMI) shielding and a method of manufacture therefor is disclosed. The semiconductor packages may house single electronic components or may be a system in a package (SiP) implementation. The EMI shielding may be provided on top of and along the periphery of the semiconductor package. The EMI shielding on the periphery may be formed of cured conductive ink or cured conductive paste disposed on sidewalls of molding that encapsulates the electronic component(s) provided on the semiconductor package. The top portion of the EMI shielding may be a laminated metal sheet provided on a top surface of the molding. The semiconductor package may further have vertical portions of the EMI shielding with conductive ink filled trenches in the molding that may separate one or more electronic components from other electronic components of the semiconductor package.

公开(公告)号：US20180089984A1

公开(公告)日：2018-03-29

申请号：US15277811

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Vijay Krishnan Subramanian ,  Steven A. Klein ,  Pramod Malatkar ,  Rajendra C. Dias ,  Aleksandar Aleksov ,  Jason P. Glumbik ,  Nadine L. Dabby

IPC: G08B21/18 ,  H05K1/02 ,  H05K1/18 ,  G01R31/28

CPC classification number: G01R31/2846 ,  H05K1/0268 ,  H05K1/189 ,  H05K2201/09263 ,  H05K2201/10151

Abstract: Techniques and mechanisms for determining a level of degradation of flexible circuitry. In an embodiment, a flexible substrate has disposed therein first circuitry and one or more components coupled thereto, the one or more components to monitor a physical property of the first circuitry. Further disposed in or on the flexible substrate are memory resources to store predefined reference information which corresponds amounts of the physical property each with a different respective level of degradation. Evaluation logic accesses the reference information to determine, based on a detected amount of the physical property, a level of degradation of second circuitry. In another embodiment, the second circuitry is more flexible, as compared to the first circuitry.

公开(公告)号：US20170181275A1

公开(公告)日：2017-06-22

申请号：US14975162

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Manish Dubey ,  Tatyana N. Andryushchenko ,  Aleksandar Aleksov ,  David W. Staines

IPC: H05K1/02 ,  H05K1/11 ,  A43B3/00 ,  H05K3/32 ,  A41D1/00 ,  H05K1/18 ,  H05K1/03

CPC classification number: H05K1/0283 ,  A41D1/002 ,  A43B3/0005 ,  H01L2224/16225 ,  H05K1/0313 ,  H05K1/0393 ,  H05K1/111 ,  H05K1/186 ,  H05K3/32

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for gradient encapsulant protection of devices in stretchable electronic. For instance, in accordance with one embodiment, there is an apparatus with an electrical device on a stretchable substrate; one or more stretchable electrical interconnects coupled with the electrical device; one or more electrical components electrically coupled with the electrical device via the one or more stretchable electrical interconnects; and a gradient encapsulating material layered over and fully surrounding the electrical device and at least a portion of the one or more stretchable electrical interconnects coupled thereto, in which the gradient encapsulating material has an elastic modulus greater than the stretchable substrate and in which the elastic modulus of the gradient encapsulating material is less than the electrical device. Other related embodiments are disclosed.

公开(公告)号：US20170179040A1

公开(公告)日：2017-06-22

申请号：US14978294

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Joshua D. Heppner ,  Mitul B. Modi ,  Anna M. Prakash

IPC: H01L23/552 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56 ,  H01L23/495 ,  H01L23/31

CPC classification number: H01L23/60 ,  H01L21/4825 ,  H01L21/56 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49524 ,  H01L23/552 ,  H01L24/27 ,  H01L24/33 ,  H01L2224/97 ,  H01L2924/3025

Abstract: An electric device and method of fabrication of that electric device is disclosed. The electric device includes one or more electrical devices attached to a substrate. The electric device further includes one or more grounding pads attached to the substrate. The electric device further includes a perforated conductive material placed on the substrate. The electric device further includes a molding compound deposited to cover the perforated conductive material, the one or more devices, and the one or more grounding pads.

公开(公告)号：US09508660B2

公开(公告)日：2016-11-29

申请号：US14618647

申请日：2015-02-10

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Emre Armagan ,  Rajendra C. Dias ,  Lars D. Skoglund

IPC: H01L29/06 ,  H01L23/00 ,  H01L23/31 ,  H01L23/12 ,  H01L21/304 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/304 ,  H01L21/563 ,  H01L23/12 ,  H01L23/3157 ,  H01L29/06 ,  H01L2224/73204

Abstract: A microelectronic die may be formed with chamfer corners for reducing stresses which can lead to delamination and/or cracking failures when such a microelectronic die is incorporated into a microelectronic package. In one embodiment, a microelectronic die may include at least one substantially planar chamfering side extending between at least two adjacent sides of a microelectronic die. In another embodiment, a microelectronic die may include at least one substantially curved or arcuate chamfering side extending between at least two adjacent sides of a microelectronic die.

Abstract translation: 可以形成具有倒角的微电子模具，用于减小当将这种微电子管芯并入微电子封装时可能导致分层和/或破裂故障的应力。 在一个实施例中，微电子管芯可以包括在微电子管芯的至少两个相邻侧面之间延伸的至少一个基本上平面的倒角侧。 在另一个实施例中，微电子管芯可以包括在微电子管芯的至少两个相邻侧面之间延伸的至少一个基本上弯曲或弧形的倒角侧。

公开(公告)号：US20160005672A1

公开(公告)日：2016-01-07

申请号：US14323077

申请日：2014-07-03

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Rajendra C. Dias ,  Patrick Nardi ,  David Woodhams

IPC: H01L23/31 ,  H01L21/56

CPC classification number: H01L21/563 ,  H01L23/24 ,  H01L24/32 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83951 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Some embodiments relate to an electronic package. The electronic package includes a substrate and a die attached to the substrate. The electronic package further includes an underfill positioned between the die and the substrate due to capillary action. A support surrounds the die. The support provides the same beneficial fillet geometry on all die edges. Therefore, the support provides similar stress reduction on all die edges. Other embodiments relate to method of fabricating an electronic package. The method includes attaching a die to a substrate and inserting an underfill between the die and the substrate using capillary action. The method further includes placing a support around the die such that the support surrounds the die.

Abstract translation: 一些实施例涉及电子包装。 电子封装包括基板和附接到基板的裸片。 电子封装还包括由于毛细管作用而位于管芯和衬底之间的底部填充物。 支架围绕着模具。 支撑件在所有模具边缘上提供相同的有益的圆角几何形状。 因此，支撑件在所有模具边缘上提供类似的应力减小。 其他实施例涉及制造电子封装的方法。 该方法包括将管芯附接到衬底并且使用毛细管作用将底部填充物插入管芯和衬底之间。 该方法还包括将支撑件放置在模具周围，使得支撑件围绕模具。

公开(公告)号：US20150179479A1

公开(公告)日：2015-06-25

申请号：US14638328

申请日：2015-03-04

Applicant: INTEL CORPORATION

Inventor： Manish Dubey ,  Rajendra C. Dias ,  Yonghao Xiu ,  Arjun Krishnan ,  Yiqun Bai ,  Purushothan Kaushik Muthur Srinath

IPC: H01L21/56

CPC classification number: H01L21/563 ,  H01L23/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particless within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures.

Abstract translation: 本说明书的实施例包括在微电子器件上处理底部填充材料之后将微电子器件附着到具有互连结构的微电子衬底的方法，其中，在将微电子器件连接到微电子器件之前，底部填充材料内的填料颗粒可能被排除离开互连结构 器件到微电子结构。 这些方法可以包括在互连结构上引入电荷，并且可以包括将互连结构放置在相对的板之间，并且在将底部填充材料沉积在互连结构上之后在相对的板之间产生偏压。

公开(公告)号：US10763220B2

公开(公告)日：2020-09-01

申请号：US16256338

申请日：2019-01-24

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Mitul B. Modi

IPC: H01L23/552 ,  H01L23/00 ,  H01L21/285 ,  H01L23/31 ,  H01L21/78 ,  H01L23/544 ,  H01L23/29 ,  H01L21/683 ,  H01L21/784 ,  H01L21/56

Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include substrate including electrical connection circuitry therein, ground circuitry on, or at least partially in the substrate, the ground circuitry at least partially exposed by a surface of the substrate, a die electrically connected to the connection circuitry and the ground circuitry, the die on the substrate, a conductive material on a die backside, and a conductive paste or one or more wires electrically connected to the ground circuitry and the conductive material.

公开(公告)号：US09991211B2

公开(公告)日：2018-06-05

申请号：US15607270

申请日：2017-05-26

Applicant: Intel Corporation

Inventor： Anna M. Prakash ,  Reynaldo Alberto Olmedo ,  Venmathy McMahan ,  Rajendra C. Dias ,  Joshua David Heppner ,  Ann Jinyan Xu ,  Sriya Sanyal ,  Eric Jin Li

IPC: H01L23/552 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/29

CPC classification number: H01L23/552 ,  H01L21/485 ,  H01L21/56 ,  H01L23/293 ,  H01L23/295 ,  H01L23/49838 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: Semiconductor packages and methods of forming semiconductor packages are described. In an example, a semiconductor package includes a shielding layer containing metal particles, e.g., conductive particles or magnetic particles, in a resin matrix to attenuate electromagnetic interference. In an example, the shielding layer is transferred from a molding chase to the semiconductor package during a polymer molding operation.