公开(公告)号：US10861861B2

公开(公告)日：2020-12-08

申请号：US16221083

申请日：2018-12-14

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sasikanth Manipatruni ,  Tanay Gosavi ,  Dmitri Nikonov ,  Sou-Chi Chang ,  Uygar E. Avci ,  Ian A. Young

IPC: H01L27/11509 ,  H01L27/11592

Abstract: An embodiment includes a system comprising: first, second, third, fourth, fifth, and sixth layers, (a) the second, third, fourth, and fifth layers being between the first and sixth layers, and (b) the fourth layer being between the third and fifth layers; a formation between the first and second layers, the formation including: (a) a material that is non-amorphous; and (b) first and second sidewalls; a capacitor between the second and sixth layers, the capacitor including: (a) the third, fourth, and fifth layers, and (b) an electrode that includes the third layer and an additional electrode that includes the fifth layer; and a switching device between the first and sixth layers; wherein: (a) the first layer includes a metal and the sixth layer includes the metal, and (b) the fourth layer includes a Perovskite material. Other embodiments are addressed herein.

公开(公告)号：US10831446B2

公开(公告)日：2020-11-10

申请号：US16145569

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Raghavan Kumar ,  Huseyin Ekin Sumbul ,  Phil Knag ,  Ram Krishnamurthy ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Abhishek Sharma ,  Ian A. Young

IPC: G06F7/544 ,  G06F17/16 ,  G06F7/501 ,  G06F9/30 ,  G06N3/04 ,  G06N3/063

Abstract: A memory device that includes a plurality subarrays of memory cells to store static weights and a plurality of digital full-adder circuits between subarrays of memory cells is provided. The digital full-adder circuit in the memory device eliminates the need to move data from a memory device to a processor to perform machine learning calculations. Rows of full-adder circuits are distributed between sub-arrays of memory cells to increase the effective memory bandwidth and reduce the time to perform matrix-vector multiplications in the memory device by performing bit-serial dot-product primitives in the form of accumulating m 1-bit×n-bit multiplications.

公开(公告)号：US10679782B2

公开(公告)日：2020-06-09

申请号：US15751111

申请日：2015-09-09

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Anurag Chaudhry ,  Ian A. Young

IPC: G11C11/16 ,  G11C11/18 ,  H01L43/00 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01F10/32 ,  H03K19/18 ,  H03K19/23 ,  H01F41/32 ,  H01L27/22

Abstract: Described is an apparatus which comprises: an input ferromagnet to receive a first charge current and to produce a first spin current; a first layer configured to convert the first spin current to a second charge current via spin orbit coupling (SOC), wherein at least a part of the first layer is coupled to the input ferromagnet; and a second layer configured to convert the second charge current to a second spin current via spin orbit coupling (SOC).

公开(公告)号：US20200098415A1

公开(公告)日：2020-03-26

申请号：US16615780

申请日：2018-07-23

Applicant: Intel Corporation

Inventor： Huichu Liu ,  Sasikanth Manipatruni ,  Ian A. Young ,  Tanay Karnik ,  Daniel H. Morris ,  Kaushik Vaidyanathan

IPC: G11C11/22 ,  H01L27/11507 ,  H01L49/02

Abstract: Described is an apparatus to reduce or eliminate imprint charge, wherein the apparatus which comprises: a source line; a bit-line; a memory bit-cell coupled to the source line and the bit-line; a first multiplexer coupled to the bit-line; a second multiplexer coupled to the source-line; a first driver coupled to the first multiplexer; a second driver coupled to the second multiplexer; and a current source coupled to the first and second drivers.

公开(公告)号：US10600957B2

公开(公告)日：2020-03-24

申请号：US15519810

申请日：2014-12-18

Applicant: INTEL CORPORATION

Inventor： David Michalak ,  Sasikanth Manipatruni ,  James Clarke ,  Dmitri Nikonov ,  Ian Young

IPC: H01L43/10 ,  G01R33/12 ,  G11B5/39 ,  H01L43/08 ,  H01L43/12 ,  G01D5/20 ,  H01L43/02

Abstract: Described is a method comprising: forming a magnet on a substrate or a template, the magnet having an interface; and forming a first layer of non-magnet conductive material on the interface of the magnet such that the magnet and the layer of non-magnet conductive material are formed in-situ. Described is an apparatus comprising: a magnet formed on a substrate or a template, the magnet being formed under crystallographic, electromagnetic, or thermodynamic conditions, the magnet having an interface; and a first layer of non-magnet conductive material formed on the interface of the magnet such that the magnet and the layer of non-magnet conductive material are formed in-situ.

公开(公告)号：US20200091308A1

公开(公告)日：2020-03-19

申请号：US16130903

申请日：2018-09-13

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Uygar Avci ,  Sou-Chi Chang ,  Ian Young

IPC: H01L29/51 ,  H01L29/78 ,  H01L27/11502 ,  H01L27/11585 ,  G11C11/22

Abstract: A capacitor is provided which comprises: a first structure comprising metal; a second structure comprising metal; and a third structure between the first and second structures, wherein the third structure comprises an improper ferroelectric material. In some embodiments, a field effect transistor (FET) is provided which comprises: a substrate; a source and drain adjacent to the substrate; and a gate stack between the source and drain, wherein the gate stack includes: a dielectric; a first structure comprising improper ferroelectric material, wherein the first structure is adjacent to the dielectric; and a second structure comprising metal, wherein the second structure is adjacent to the first structure.

公开(公告)号：US20190386120A1

公开(公告)日：2019-12-19

申请号：US16009064

申请日：2018-06-14

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sasikanth Manipatruni ,  Tanay Gosavi ,  Sou-Chi Chang ,  Dmitri Nikonov ,  Ian A. Young

IPC: H01L29/66 ,  H01L29/82 ,  H01F10/32 ,  G11C11/16

Abstract: An apparatus is provided which comprises: a first stack comprising a magnetic insulating material (MI such as., EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, or graphene; a second stack comprising an MI material and a TMD, wherein the first and second stacks are separated by an insulating material (e.g., oxide); a magnet (e.g., a ferromagnet or a paramagnet) adjacent to the TMDs of the first and second stacks, and also adjacent to the insulating material; and a magnetoelectric material (e.g., (LaBi)FeO3, LuFeO3, PMN-PT, PZT, AlN, or (SmBi)FeO3) adjacent to the magnet.

公开(公告)号：US10483026B2

公开(公告)日：2019-11-19

申请号：US15569978

申请日：2015-06-24

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Anurag Chaudhry ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: G11C11/00 ,  H01F10/32 ,  H01L43/10 ,  H01L43/08 ,  H03K19/16 ,  G11C11/16 ,  G11C11/155 ,  H03K19/18 ,  H01F10/26

Abstract: Described is an apparatus which comprises: an input ferromagnet to receive a first charge current and to produce a corresponding spin current; and a stack of metal layers configured to convert the corresponding spin current to a second charge current, wherein the stack of metal layers is coupled to the input magnet.

公开(公告)号：US10333523B2

公开(公告)日：2019-06-25

申请号：US15567945

申请日：2015-05-28

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri Nikonov ,  Ian A. Young

IPC: H03K19/21 ,  H01L43/08 ,  H03K19/18 ,  H01L43/04

Abstract: Described is an apparatus which comprises: a first layer formed of a material that exhibits spin orbit torque effect; a second layer formed of material that exhibits spin orbit torque effect; and a magnetic tunneling junction (MTJ) including first and second free magnetic layers, wherein the first free magnetic layer is coupled to the first layer and wherein the second free magnetic layer is coupled to the second layer.

公开(公告)号：US20190043560A1

公开(公告)日：2019-02-07

申请号：US16146473

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Abhishek Sharma ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Ram Krishnamurthy ,  Ian A. Young

IPC: G11C11/418 ,  G06F7/544 ,  G06F9/30 ,  G11C13/00 ,  G11C11/419

Abstract: A memory circuit has compute-in-memory circuitry that enables a multiply-accumulate (MAC) operation based on shared charge. Row access circuitry drives multiple rows of a memory array to multiply a first data word with a second data word stored in the memory array. The row access circuitry drives the multiple rows based on the bit pattern of the first data word. Column access circuitry drives a column of the memory array when the rows are driven. Accessed rows discharge the column line in an accumulative fashion. Sensing circuitry can sense voltage on the column line. A processor in the memory circuit computes a MAC value based on the voltage sensed on the column.