公开(公告)号：US12237832B2

公开(公告)日：2025-02-25

申请号：US17479963

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Miguel Bautista Gabriel ,  Sriram Vangal ,  Patrick Koeberl ,  Pratik Patel ,  Muhammad Khellah ,  James Tschanz ,  Carlos Tokunaga ,  Suyoung Bang

IPC: H03K19/177 ,  G01R31/28 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/17768 ,  H03K19/17784

Abstract: A detection circuit includes a tunable delay circuit that generates a delayed signal and that receives a supply voltage. The detection circuit includes a control circuit that adjusts a delay provided by the tunable delay circuit to the delayed signal. The detection circuit includes a time-to-digital converter circuit that converts the delay provided by the tunable delay circuit to the delayed signal to a digital code and adjusts the digital code based on changes in the supply voltage. The control circuit causes the tunable delay circuit to maintain the delay provided to the delayed signal constant in response to the digital code reaching an alignment value. The detection circuit may continuously monitor timing margin of a data signal relative to a clock signal and update the digital code in every clock cycle. The detection circuit may be a security sensor that detects changes in the supply voltage.

公开(公告)号：US11828776B2

公开(公告)日：2023-11-28

申请号：US16829582

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Pratik Patel ,  Sriram Vangal ,  Patrick Koeberl ,  Miguel Bautista Gabriel ,  James Tschanz ,  Carlos Tokunaga

IPC: G01R19/165 ,  G06F21/75 ,  H03K5/00 ,  H03K3/037 ,  H03K19/21 ,  H01L23/00 ,  G06F11/07

CPC classification number: G01R19/16533 ,  G06F11/0736 ,  G06F11/0757 ,  G06F11/0772 ,  G06F21/755 ,  H01L23/576 ,  H03K3/037 ,  H03K5/00 ,  H03K19/21 ,  H03K2005/00058 ,  H03K2005/00078

Abstract: A voltage detection circuit includes a tunable delay circuit that receives a supply voltage and that generates a delayed signal in response to an input signal. A control circuit causes a first adjustment in a delay provided by the tunable delay circuit to the delayed signal. An error detection circuit generates an error indication in an error signal in response to a change in a timing of the delayed signal relative to a clock signal caused by the first adjustment in the delay provided to the delayed signal. The control circuit causes a second adjustment in the delay provided by the tunable delay circuit to the delayed signal in response to the error indication. The error detection circuit causes the error signal to be indicative of the supply voltage reaching a threshold voltage after the second adjustment in the delay.

公开(公告)号：US11281281B2

公开(公告)日：2022-03-22

申请号：US16956447

申请日：2018-02-28

Applicant: Intel Corporation

Inventor： Jayanth M. Devaraju ,  Vivek De ,  Sriram Vangal

IPC: G06F1/32 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296

Abstract: Circuitry is provided to control a performance level of a processing device depending on two or more operating points of the processing device. An operating point has a corresponding frequency and a corresponding voltage. The performance-level control circuitry arranged to cross-multiply parameters corresponding to a first operating point and a second, different operating point of the processing device. A relative energy expenditure of the first operating point and the second operating point is determined based on the cross multiplication. An operating point of the processing device is selected depending on the determined relative energy expenditure. An apparatus having the performance level control circuitry, machine readable instructions for implementing the performance level control and a corresponding method are also provided.

公开(公告)号：US10530254B2

公开(公告)日：2020-01-07

申请号：US15632086

申请日：2017-06-23

Applicant: INTEL CORPORATION

Inventor： Khondker Ahmed ,  Vivek De ,  Nachiket Desai ,  Suhwan Kim ,  Harish Krishnamurthy ,  Xiaosen Liu ,  Turbo Majumder ,  Krishnan Ravichandran ,  Christopher Schaef ,  Vaibhav Vaidya ,  Sriram Vangal

IPC: H02M3/158 ,  H02M1/08 ,  H02M1/00

Abstract: Embodiments described herein concern operating a peak-delivered-power (PDP) controller. Operating a PDP includes calculating the new power output value from the output voltage value and the output current value, determining whether the new power output value is greater than the previous power output value to determine whether the voltage regulator is outputting a maximum power output, based on a determination that the new power output value is greater than the previous power output value, providing an instruction to a duty generator to increase a duty cycle of the voltage regulator, based on a determination that the new power output value is not greater than the previous power output value, providing an instruction to the duty generator to decrease the duty cycle of the voltage regulator, and replacing the previous power output value with the new power output value.

公开(公告)号：US20190227750A1

公开(公告)日：2019-07-25

申请号：US16370007

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Srikanth Srinivasan ,  Richard Coulson ,  Rajesh Sundaram ,  Bruce Querbach ,  Jawad B. Khan ,  Shigeki Tomishima ,  Sriram Vangal ,  Wei Wu ,  Chetan Chauhan

IPC: G06F3/06

Abstract: Technologies for performing tensor operations in memory include a memory comprising media access circuitry coupled to a memory media having a cross point architecture. The media access circuitry is to access matrix data from the memory media, perform a tensor operation on the matrix data, and write, to the memory media, resultant data indicative of a result of the tensor operation.